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QRC Parasitic Extraction Issue (netlist has source/drain flipped on many instances)

jimstuy

Hi,

   I am working on a analog design in Cadence IC6.1.4.500.5, and I have completed the layout of the chip with DRC, LVS, floating gate check that is clean (I amworking with IBM's CMRF7SF process).After I ran Assura QRC to generate av_extracted, and av_analog_extracted views I go back into my testbenches to run toplevel sims with these new views, and I am running into problems.

   I am comparing the netlist with extracted views, and I noticed that on many of the NMOS and PMOS devices, the source and drain is flipped from what I intended them to be in my design. For example, I expect N1 to have a netlist of N1(D G S B) according to my schematics, and instead of that, the parasitic netlist of the instance N1 has a netlist of N1(S G D B). Wondering why that's the case. I passed LVS, and this only shows up in av_extracted and analog_av_extracted views... Thanks for any tip/advice from you!

Parents

  •  Morning Quek, and hi everyone.

     I am still experiencing issues here with my extraction verification. But I think I've found the rot cause. I 've been playing with the threshold to which a parasitic R gets saved, and I am at a point where I set the value such that only one parasitic R gets extracted and becomes part of the netlist of my overall av_extracted design. I then exhaustively check my netlist for discrepancies.

      Here's what I found: My design is a fully differential design, and after running a DC sim of my extracted netlist, my outputs rail. This gave me the idea to look in a particular circuit block (common mode feedback amp, but it's not central to this discussion) What I find is that: Say I have a resistor RRR0 connecting to a mosfet called TN9. The netlist for TN9 shows the following:

      TN9( net0  \1\:SH5\voutcm  net1  net1), and the resistor netlist is showing up as RRR0 ( SH5\voutcm ....)

      There's the problem... the addition of "\1\:" in the gate terminal of TN9 effectively disconnected the resistor from the nmos's gate. Is anyone else aware of this issue or any potential fixes? 

      I use multisheet in cadence to document my design, so the TN9, and RRR0 both appear on sheet 5 of the design. Hence the SH5\ designation. 

      I then went back to the Assura QRC menu and chose C extraction only. My sims work fine, and my netlist for TN9 and RRR0 both have the same netname called "SH5\voutcm". In this case, there was no random insertion of "\1\:" into the netname...

      

Reply

  •  Morning Quek, and hi everyone.

     I am still experiencing issues here with my extraction verification. But I think I've found the rot cause. I 've been playing with the threshold to which a parasitic R gets saved, and I am at a point where I set the value such that only one parasitic R gets extracted and becomes part of the netlist of my overall av_extracted design. I then exhaustively check my netlist for discrepancies.

      Here's what I found: My design is a fully differential design, and after running a DC sim of my extracted netlist, my outputs rail. This gave me the idea to look in a particular circuit block (common mode feedback amp, but it's not central to this discussion) What I find is that: Say I have a resistor RRR0 connecting to a mosfet called TN9. The netlist for TN9 shows the following:

      TN9( net0  \1\:SH5\voutcm  net1  net1), and the resistor netlist is showing up as RRR0 ( SH5\voutcm ....)

      There's the problem... the addition of "\1\:" in the gate terminal of TN9 effectively disconnected the resistor from the nmos's gate. Is anyone else aware of this issue or any potential fixes? 

      I use multisheet in cadence to document my design, so the TN9, and RRR0 both appear on sheet 5 of the design. Hence the SH5\ designation. 

      I then went back to the Assura QRC menu and chose C extraction only. My sims work fine, and my netlist for TN9 and RRR0 both have the same netname called "SH5\voutcm". In this case, there was no random insertion of "\1\:" into the netname...

      

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