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How to do analog modeling with verilog -A

Analog Design

Hi

   I wan to add a random generator verilog-A file using  vertuoso @ analog envouirnment and vertuoso spectre simulator to simulate analog circuit . But I do't knw the procedure to do it . (provided I have  .va file ). Can any1 help me?

  • First things first. There is no tax on characters in this forum, so please write proper English. Some of us struggle to know what "any1" means or at least find it extremely hard to read.

    Do File->New->CellView and fill in the library and cell name for the module you wish to create. Then set the type to "VerilogA" (it will set the viewName to "veriloga" automatically - although you could change that to something else if you really want).

    An editor will be launched. You can set your favourite editor in the CIW or .cdsinit by typing (say):

      editor="nedit"

    before doing this File->New->CellView.

    Edit the code as you wish. Save and exit the editor, and it will be syntax checked and if OK will ask you to create a symbol.

    Place an instance of that symbol in your circuit, start ADE, run the simulation, and that's it.

    There are also examples (including a random generator) in the ahdlLib library which can be added to your cds.lib by adding the line:

     ahdlLib         $(inst_root_with:tools/dfII/bin/dbAccess)/tools/dfII/samples/artist/ahdlLib

    (that should work in both IC5141 and IC61X releases).

    Regards,

    Andrew.

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