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Regarding behavioural modelling of analog design

Analog Design

 Hi,

     I have a dout wheather we can retrive back the exact circuit (Schematic) from behavioural modelling of analog Block(designed using verilog-A). Because whatever the behavioural design  we do in digital using verilog , we able to get RTL veiw of our design . Is it possible in case of analog Block modelling?

  • Even with digital, you normally can't go from behavioural to RTL. You can write RTL and synthesize gates from it. There are some tools (like CtoS) which can synthesize from C, but in general you can't synthesize arbitrary digital behavioural models.

    Synthesis from Analog Models is not something that is really available (there have been some forays into Analog Synthesis for specific types of design, but nothing general, and nothing that has been particularly successful).

    Regards,

    Andrew.

  • Hi Andrew,
    thanks for your clarification .
    >
    > Even with digital, you normally can't go from behavioural to RTL. You can
    > write RTL and synthesize gates from it. There are some tools (like CtoS)
    > which can synthesize from C, but in general you can't synthesize arbitrary
    > digital behavioural models.
    > Synthesis from Analog Models is not something that is really available
    > (there have been some forays into Analog Synthesis for specific types of
    > design, but nothing general, and nothing that has been particularly
    > successful).
    > Regards,
    > Andrew.
    >
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