Is it possible to use a netset to redefine a global in a spectre model file?

I have a symbol that has an input and an output.  It is an inverter with no supply connections on the symbol.  It is called inv_1_v50.  It is show on my simulation schematic that is attached.

I have a verilogA model of an inverter that is called bh60a_inv_min_nl.  It has the input and output ports, but also has the supply nodes.  Also the port names don't match between the two.  It's code is as follows:

`include "constants.vams"
`include "disciplines.vams"

//definition internal constants

`define tdel 1n
`define trise 1n
`define tfall 1n

module bh60a_inv_min_nl(x, gnd, vdd, a);

output x;
electrical x;
inout gnd;
electrical gnd;
inout vdd;
electrical vdd;
input a;
electrical a;

parameter real R_out =1 from (0:inf);  //Output resistance of comparator;
parameter real cap_out =0.001p from (0:inf); //Output capacitance;


real logic_out, Vout_int, out_int, vtrans;

analog begin
      @(initial_step)
      begin
             vtrans    = V(vdd,gnd)/2.0;
             logic_out = !(V(a, gnd) > vtrans);
      end
        vtrans    = V(vdd,gnd)/2.0;
            logic_out = !(V(a, gnd) > vtrans);

        
        @(cross(V(a,gnd)-vtrans - 0.5,+1)) begin
                
            logic_out=0;
        
        end      
             
                
        @ (cross(V(a,gnd)-vtrans + 0.5,-1)) begin
        
            logic_out=1;
        
        end
        
    
    out_int = V(vdd,gnd)*transition(logic_out,`tdel,`trise,`tfall);
    I(x,gnd) <+ ((-out_int + V(x,gnd))/R_out)+(ddt(cap_out*V(x,gnd)));
end
endmodule




// release definitions of internal constants

`undef tdel
`undef trise
`undef tfall

I wanted to link the symbol to the verilogA with a model file such that I don't have to rewrite the verilogA code, or have to update the symbol (I have a lot of cells to do this on, and potentally I need to do it across a lot of designs).  Here is the model file I wrote:

//title
simulator lang = spectre    
global 0 gnd! vdd
ahdl_include "/home/ffmygt/models/logic_models.va"
subckt inv_1_v50 X A
    //R1 (X A) resistor r=1
    I1 (X gnd! vdd A) bh60a_inv_min_nl
ends inv_1_v50

 I then selected this model file with the config view for simulation.  This works (in ams, but I can't make it work in spectre), but I am unable to apply a netset for the vdd node in the model file on my schematic.  I tried to netset vdd=va on the symbol (as shown in the attachment), but vdd in the model file still ends up connected to vdd on the schematic.

Is there some way to apply a netset to a global node in a model file?  Maybe there is some other syntax I should be using in the model file to pass the nodes not shown on the symbol?

Thanks