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transient noise analysis

naderi

 Hello all,

 In ADE, transient analysis allows to incorporate transient noise in the simulation. It however needs to define noisefmax parameter.

If a continuous-time analog design is concern, there is no limit for the maximum frequency of the noise in reality. So, Why is there such a parameter?

In my design I have tested for different noisefmax, and it seems the higher noisefmax, the lower SNR at the output. I wonder how to set this parameter to have a realistic noise estimation. Is there any idea?

 I appriciate your comments.

Thanks,

Ali

Parents

  •  Thank you very much for your time and the detailed description.

    From what you mentioned the transient noise is therefore best for non-periodic and larg signal circuits, when noise is white. I think my circuits have the same situation.

    Is the filcker noise considered in this analysis?

    I have already optimized this design using noise ananlysis, and tried to get V**2/Hz < -138dB at all corners. Now when simulating using transient noise, I see that the output noise is highly depends on the noisefmax. For sure the circuit has finite bandwidth due to parasictics. It is a part of bigger design with discrete-time circuits with a sampling frequency of fs=5MHz (other parts of the design are verilogA models and do not generate noise). Changing noisefmax from fs to 128 fs procudes confusing results at different corners as following (noisefmin is not set).

    Corners    tt      ss       sf        fs        ff              noisefmax
    SNR    76.9    82.2    75.5    84.3    84.6    dB    fs = 5MHz
    SNR    82.3    71.1    72.3    70.2    75.3    dB    16xfs
    SNR    73.9    71.0    73.1    78.2    73.1    dB    128xfs
     

    In all the simulations the maximum step size is 1ns, which is much less than 1/fs. However, in some corners increasing the noisefmax reduces the total output noise. Moreover, for those corners that output noise has increased vs noisefmax, trends are not similar.

    I wonder if this bahavior can be explain for one circuit. It seems simulator is changing the paramters nonlinearly based on noise bandwidth and makes it difficult to trust the reseults.

    Any idea?

    Thanks,

    Ali

Reply

  •  Thank you very much for your time and the detailed description.

    From what you mentioned the transient noise is therefore best for non-periodic and larg signal circuits, when noise is white. I think my circuits have the same situation.

    Is the filcker noise considered in this analysis?

    I have already optimized this design using noise ananlysis, and tried to get V**2/Hz < -138dB at all corners. Now when simulating using transient noise, I see that the output noise is highly depends on the noisefmax. For sure the circuit has finite bandwidth due to parasictics. It is a part of bigger design with discrete-time circuits with a sampling frequency of fs=5MHz (other parts of the design are verilogA models and do not generate noise). Changing noisefmax from fs to 128 fs procudes confusing results at different corners as following (noisefmin is not set).

    Corners    tt      ss       sf        fs        ff              noisefmax
    SNR    76.9    82.2    75.5    84.3    84.6    dB    fs = 5MHz
    SNR    82.3    71.1    72.3    70.2    75.3    dB    16xfs
    SNR    73.9    71.0    73.1    78.2    73.1    dB    128xfs
     

    In all the simulations the maximum step size is 1ns, which is much less than 1/fs. However, in some corners increasing the noisefmax reduces the total output noise. Moreover, for those corners that output noise has increased vs noisefmax, trends are not similar.

    I wonder if this bahavior can be explain for one circuit. It seems simulator is changing the paramters nonlinearly based on noise bandwidth and makes it difficult to trust the reseults.

    Any idea?

    Thanks,

    Ali

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