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NC-Verilog netlister setttings to output single netlist (not hierarchy-ihnl/ based)

jagarcia85
Hi there,

Apologies if this had been posted already.

I have been successful at generating a single, plain Verilog netlist from a config view (including verilog, functional, schematics, etc. views) in the past.
Now, for a different project, I am in need for the same thing and the netlister keeps yielding an ihnl-based netlist.
Before it did as well, but it would create a single netlist file besides the ihnl dir structure... now I can only get it to produce the ihnl ones, not the single file.

Is there a swtich or setup I am missing, or a script, procedure to follow to obtain a plain single netlist?  
Thanks in advance!

  • This is covered in Solution 1839821

    Put vlogifCompatibilityMode="4.0" in your .simrc file (e.g. working dir) or even by typing it in the CIW, before creating the netlist in the interface.

    Best Regards,

    Andrew

     

  •  Hi Andrew,

    I used your command and NC Verilog is able to generate a single netlist. However, I have some cells that used in my schematic are from a library called TSMC, which is not refered in NC.Therefore, the generated netlist includes some modules that no verilog simulators can compile through. Could you please tell me how to refer a library in the NC verilog environment so the generated netlist will be completely flatten? I'm using Virtuoso 6.1.5

    Thank you very much!

  • I don't understand your question. What do you mean "the generated netlist includes some modules that no verilog simulators can compile through"? If no verilog simulator can compile it, doesn't that mean that it's incorrect syntax? I also don't know what you mean by "Is not refered in NC".

    Please clarify your question!

    Regards,

    Andrew.

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