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Generate Schematic from Verilog Netlist - undefined function ipcBeginProcess

gwong

Hi,

 

I am trying to create a schematic view from a gate-level verilog netlist from the "File-> Import -> Verilog... " menu in the CIW window.  I'm getting the following error:

*Error* eval: undefined function - ipcBeginProcess
ERROR (VERILOGIN-205): An internal memory error has occurred. Exiting.

 I've checked memory usage and it appears to be fine.

 I'm using IC6.1.5

 

Thanks for your help.

Gary

  • Hi Gary,

    Are you using the first customer shipment (FCS) version of IC6.1.5, or an ISR (e.g. ISR1 or ISR2) (what does getVersion(t) report) ?

    Does everything else work correctly?  Are you running "virtuoso" from the Unix prompt to start the session, or something else? I am concerned that the virtuoso installation does not seem to have the ipcBeginProcess function defined - it is a low-level built-in function, not even a function that is written in SKILL and loaded through a context file.  So my thoughts are, if ipcBeginProcess is really missing, is the installation "complete"?  I did not see the above error in our database, by the way.

    Regards,

    Lawrence.

  •  Hi Lawrence,

    Thanks for your prompt response.

    getVersion(t) reports "sub-version  IC6.1.5-64b.72 "

     We've only used this version for about a week or 2 now and everything seems to be working, except, waveform viewer problem (I've been notified of a fix coming in June, I think). I type "virtuoso" at the Unix prompt to start the session. 

    I will check with my IT to see if there were any issues with the installation.

     Regards,

    Gary

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