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  3. Layout of Triple Well NFET without Pcell

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Layout of Triple Well NFET without Pcell

bnugent
bnugent over 14 years ago
Hello all,

I was recently tasked with drawing Pcells of nfetxs layer by layer. I successfully completed a generic nfetx, but am having difficultly with the nfettwx. I have gotten the triple well (nfettwx) to pass DRC with no errors, however, when I run the LVS (Assura) errors pop up. They are:

*ERROR* Device 'nfettw(Generic)' on Schematic is unbound to any Layout device.
*ERROR* Device 'nfet(Generic)' on Layout is unbound to any Schematic device.

I believe the errors indicate that: In layout it recognizes the nfetx lying in the triple well, but does not recognize that it is apart of the whole block, the nfettwx. In the schematic it recognizes that there should be a nfettwx in the layout but does not see it there. My question, has anyone tried drawing an nfettwx layer by layer and run into this problem? I'm relatively new to this version of cadence (IC6.1.4) so any help would be appreciated!

 Brian N
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  • Andrew Beckett
    Andrew Beckett over 14 years ago
    Brian,

    Since this is question is more related to the technology you're using, or rather the specific design kit version (or rule deck version), rather than the tool version, nobody is likely to be able to help you unless you provide that information.

    You've not given any clue whatsoever as to the technology you're using, let alone design kit/ruleset version.

    Kind Regards,

    Andrew
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  • bnugent
    bnugent over 14 years ago
    Andrew, Thanks for the advice. I'll be more detailed next time. Brian
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