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Layout of Enclosed Gate Transistors (EGTs or ELTs)

bnugent

 Hello,

 I'm designing an enclosed layout transistor but can not pass both DRC and LVS.

I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura.

Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly appreciated

 

Brian

Parents

  • Hi Brian

    Hope that you do not mind the following the following minor correction:

    "my simulator is Assura" -> "my verification tool is Assura". : )

    Actually it would be best to contact your local Cadence support for this issue as I think a proper testcase is needed for the troubleshooting. If you have any difficulty in get official Cadence support, please upload the following files in the Assura run directory:

    yourDesign.cls
    yourDesign.log
    yourDesign.erc
    yourDesign.cfr (if it exists)

    Thanks
    Quek

Reply

  • Hi Brian

    Hope that you do not mind the following the following minor correction:

    "my simulator is Assura" -> "my verification tool is Assura". : )

    Actually it would be best to contact your local Cadence support for this issue as I think a proper testcase is needed for the troubleshooting. If you have any difficulty in get official Cadence support, please upload the following files in the Assura run directory:

    yourDesign.cls
    yourDesign.log
    yourDesign.erc
    yourDesign.cfr (if it exists)

    Thanks
    Quek

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