Stats

  • Locked Locked
  • Replies 7
  • Subscribers 126
  • Views 22964
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

problem using CDL in to import a spice netlist ?

isazulkc

Hi All,

I am using " CDL->Import " to import a spice netlist in order to create a corresponding schematic and make some simulations.

 When I import the .spi file with or without any DeviceMap file, MOS devices are imported in the schematic, but not diodes and  resistors. Aslo, the importation doesn't differenciate 3.3V MOS (3Vnfet, 3Vpfet) devices from 1.8V MOS (nfet, pfet) devices. How to differentiate them?

Any help will be very appreciated.

here are the related files:

 ******************************
SpiceFile : Example.spi
*******************************

.GLOBAL VDD VSS VD33

.SUBCKT EXAMPLE OUT IN
M_0 NET_1 IN VSS VSS N W=33U L=0.4U
M_2 OUT NET_1 VSS VSS ND W=22U L=0.3U
M_1 NET_1 IN VDD VDD P W=30U L=1U
M_3 OUT NET_1 VD33 VD33 PD W=44U L=2U
D_0 OUT VSS DB AREA=613.134P
D_1 VD33 OUT DP AREA=161.84P
D_3 VSS VD33 D1 AREA=590.4P
R_0 VDD NET_1 1221.24
R_1 NET_1 VSS 656.98
*PGATE NGATE
.ENDS EXAMPLE

 ******************************
DeviceMap File :
*******************************

devMap := nfet N
propMatch := subtype NM
termMap := D D G G S S B B
propMap := W W L L
addProp := model nch

devMap := nfet ND
propMatch := subtype NV
termMap := D D G G S S B B
propMap := W W L L
addProp := model nch3

devMap := pfet P
propMatch := subtype PM
termMap := D D G G S S B B
propMap := W W L L
addProp := model pch

devMap := pfet PD
propMatch := subtype PV
termMap := D D G G S S B B
propMap := W W L L
addProp := model pch3

devMap := diode DB
termMap := PLUS PLUS MINUS MINUS

devMap := diode DP
termMap := PLUS PLUS MINUS MINUS

devMap := diode DN
termMap := PLUS PLUS MINUS MINUS

devMap := diode D1
termMap := PLUS PLUS MINUS MINUS

devMap := resistor RES
propMatch := r 1221.24
termMap := PLUS PLUS MINUS MINUS

devMap := resistor RES
propMatch := r 656.987
termMap := PLUS PLUS MINUS MINUS

******************************
log File : ni.log
*******************************

 ##########################

Reference Libraries...
cmosp18
tpz973gv_280a
##########################
---- Device-mapping enabled ----


1 subckt(s) found in the netlist file.


==========================
 Subckt: EXAMPLE
==========================

Created the CV EXAMPLE->netlist_tmp.

#####################################
 MOS Instance: M_3
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview pfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview pfet->symbol.

instName->'M_3' is created.
The net 'OUT' of instance 'M_3' has been connected to the terminal 'D'.
The net 'NET_1' of instance 'M_3' has been connected to the terminal 'G'.
The net 'VD33' of instance 'M_3' has been connected to the terminal 'S'.
The net 'VD33' of instance 'M_3' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_1
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview pfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview pfet->symbol.

instName->'M_1' is created.
The net 'NET_1' of instance 'M_1' has been connected to the terminal 'D'.
The net 'IN' of instance 'M_1' has been connected to the terminal 'G'.
The net 'VDD' of instance 'M_1' has been connected to the terminal 'S'.
The net 'VDD' of instance 'M_1' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_2
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview nfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview nfet->symbol.

instName->'M_2' is created.
The net 'OUT' of instance 'M_2' has been connected to the terminal 'D'.
The net 'NET_1' of instance 'M_2' has been connected to the terminal 'G'.
The net 'VSS' of instance 'M_2' has been connected to the terminal 'S'.
The net 'VSS' of instance 'M_2' has been connected to the terminal 'B'.

#####################################
 MOS Instance: M_0
#####################################

...Searching for a valid mapping in the dev-map file...
        ...did not find a valid mapping.
Searching for the master cellview nfet->symbol in ref libs...
    ...in cmosp18: Bingo! Found the master cellview nfet->symbol.

instName->'M_0' is created.
The net 'NET_1' of instance 'M_0' has been connected to the terminal 'D'.
The net 'IN' of instance 'M_0' has been connected to the terminal 'G'.
The net 'VSS' of instance 'M_0' has been connected to the terminal 'S'.
The net 'VSS' of instance 'M_0' has been connected to the terminal 'B'.
INFO (CDLIN-54): CDL In successfully created the schematic view tpz973gv_280a.EXAMPLE::netlist. Read the log file
'conn2sch_EXAMPLE.log' for more information.
 
  TOTAL CELLS #: 1

       *************************    
       ******   SUMMARY   ******    
       *************************    

    CELL                           TERMINAL #    NET #      INSTANCE #   
  -----------------------------------------------------------------------------
    EXAMPLE                          4             6          4       

********************************************************************************************************************************************

Even if I change the original resistor description R_0 VDD NET_1 1221.24 to R_0 VDD NET_1 RES r=1221.24 the problem is still the same for resistor importation.

 Thanks for your support !!!

  • Add two lines above the .SUBCKT:

    *.BIPOLAR
    *.DIOAREA

    without that, it omits the diodes and resistors from the netlist (this is historical from Dracula days; since the Dracula CDL parser is used in IC5141, you have to comply with CDL rules). The *.DIOAREA is to tell it to read the diode area.

    Then you'll need to propMatch the subtype on the diodes. You'll also want to omit the propMatch on the resistor values.

    Regards,

    Andrew.

  • Hi Andrew,

    Thanks, when I added these two lines, resistors and diodes were successfully imported without the DeviceMap file.  However, with the previous DeviceMap file it didn't work because I did not really understand the DeviceMap file syntax. Now I understand better. So, I totally change the DeviceMap file and it works better now, 1.8V and 3.3V MOS are differentiate and all the components are imported.

    Thanks again for your support!

    Best Regards

    KC

  •  Hi Andrew,

          You seems to help alots of customer who're using cadence tools!! Kudo to you. I have a question, when I do spicein, how do I make a schematic with global inherited connection. I tried to specify in spice mapping file as follow but it didnt work.

     

     devSelect := VDD VDD
            propMatch := VDD
            inhTerms := VDD!
            propMap := VDD!
            addProp := VDD!

    devSelect := VSS VSS
            propMatch := VSS
            inhTerms := VSS!
            propMap := VSS!
            addProp := VSS!

    devSelect := VPW VPW
            propMatch := VPW
            termOrder := VPW
            inhTerms := VPW!
            propMap := VPW!
            addProp := VPW!

    devSelect := VNW VNW
            propMatch := VNW
            termOrder := VNW
            inhTerms := VNW!
            propMap := VNW!
            addProp := VNW!

     I searched through the whole cadence but could not find the format for the Global Inherited Connection for mapping table.

     

  • Please don't append onto old threads, as outlined in the Forum Guidelines.

    There is currently only limited support for Inherited Connections in SPICE IN. If you look in <ICinstDir>/doc/transrefOA/transrefOA.pdf and search for the bit headed "Inherited Connections Supported" it explains what is supported. Essentially it can handle the situation where your netlist has more terminals than the symbol, and can convert those additional terminals into netSet properties.

    If you're expecting to be able to create netExpr properties for some nets, that isn't (I believe) supported yet - there are a few CCRs related to that. I suggest you contact customer support to get your request in there.

    In addition, you might find the SKILL in this solution useful - it can convert globals into inherited connections.

    Regards,

    Andrew.

     

  • Hi Andrew,

    Thanks for the skill code and information.

    Best Regards
    Tan
  • Hi Andrew,

    Thanks you very much for your Helps in this Forum, they’re very valuable and helpful.  I’d like to ask you a question about the Export DEF in cadence 5.1 and 6.1, I have an Mixed Signal Block (digital content) and the  block shape is  Non-Rectangle (Rectilinear). I tried to write out the DEF from 6.1 and 5.1 but I got a Rectangle Coordinate in the DIE SIZE statements with only 2 coordinates. Is Cadence 6.1 support  Non-Rectangular shapes.

    Thanks

    Tan

  • Hi Tan,

    To answer your question, yes IC61x does support a rectilinear boundary - the DEF version needs to be 5.6 or greater, so unfortunately IC51x does not support a rectilinear boundary, only rectangular. Check out Solution Article 11670188, I think it covers your most recent question.

    Regards,

    Lawrence.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.