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ASSURA: want it to error is a particular cell name doesn't match

brendatx

I have 10 variations of a bit cell in layout and schematic.  The 10 variations of layout/schematic have unique names.  The 10 variations are all electrically the same just slightly different layout rules used for  fab testing purposes.  I want to be able to LVS the top levels and receive an error if this particular bit cell doesn't match the corresponding schematic's name.

 Example:

If ChipLevel1 accidently points to BitCell2, right now it will lvs correctly because technically BitCell1 and BitCell2 are electrically the same.  I need that to error and tell me the cell names are not matching.

 

Thanks!

  • Do they have different names, i.e., labeled? Try to use binding rule to bind the correspondences.

  • The schematics and layouts have different cell names.

     In my top level named "Top1", it should have an array of "Bit1".  The Top1 schematic is created this way, as well as the layout.  BUT, I want to be able to catch any mistakes that if "Top1" layout actually had an array of "Bit2" instead of "Bit1".  Will a binding file do this?  I thought the binding file only helped LVS match those schematics to a differently named layout. 

  • Oh to clarify my first sentence, the layout and schematic have the same names.  It is the upper levels I am concerned about... if an upper level has the wrong bit instantiated.

  • [BUT, I want to be able to catch any mistakes that if "Top1" layout actually had an array of "Bit2" instead of "Bit1".]

    If BIT1 and BIT2 are different layout arrays (instances), LVS won't match anyway. The tool supposes to get BIT1 from scheamtic tied to the same layout instance.

     You are correct about the binding rule usage.

     I am taking vacation soon. If this does not clarify the problem/question you have, file a SR to get AE to work with you.

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