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Measuring loop gain of 6T SRAM during write operation

Ivan13
Hi All I have measured loop gain of SRAM during hold operation (during hold it is just two inverters) for different initial conditions on two internal nodes ( Q and Q') and as expected, the two stable solutions will be with loop gain lower than 1. Loop gain is measured by putting AC source on one of the internal connections and measuring Vout/Vin of this AC source. DC operating point is secured by putting DC source with large inductance at two internal voltage Q and Q'. I tried to do the same for write operation which means to add 2 access transistors. I would expect to see only one solution (vdd,0) or (0, vdd) with loop gain

  • That's all very interesting, but did you have a question? Make sure you provide enough information when you ask your question to increase the likelihood of somebody being able to answer it.

    Regards,

    Andrew.

  • Sorry, I wasn't clear. The title should be "How should I measure loop gain for write operation?" The results I get doesn't make sense, so my original question was how should I measure the loop gain Hope now it is clear Regards, Ivan

  • You could try using spectre's stb analysis to measure the loop gain; you just need an iprobe or 0V vsource in the feedback loop to act as the measurement device for the stability analysis. I'm afraid I'm unfamiliar with the specifics of SRAM design to be able to give you anything more specific. The analysis will then allow you to plot the loop gain whilst keeping the loop closed without disturbing anything.

    Andrew.

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