Stats

  • Locked Locked
  • Replies 0
  • Subscribers 125
  • Views 13724
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Unable to generate netlist from the schematic

Joseph044

Hi,

I am working on a ADC which has both analog and digital components. I have done the entire deisgn using cadence virtuoso schematic.  Now i wanted to do custom layout for the analog parts and generate the layout for the digital parts using cadence encounter and combine the two layouts and make the connections.. is this possible?(integrating both together)

I was trying to generate the netlist for the digital schematic but it was showing me this error: can anyone help me on this:

ERROR(OSSHNL-369): Instance 'i1' in cellview "D_CELLSL/DFRLX1/functional' is bound to placed master 'VLG_PRIMITIVES/u1_fd4/symbol'.

However, OSS has determined that it is not a valid placed master.

  how can i proceed on this

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.