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Compiling ahdlcmi module library

naderi

Hi all,

Using ADE-XL, I am runing DC analysis over many corners. For each corner spectre performs as following, which is time consuming.

1-What are these steps for?

2-Is it possible to to do the compilation once for all corners?

3-what are bsource?

Thanks,

 

 Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/bsource_2.input.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/bsource_2.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 14 s (elapsed).
Installed compiled interface for bsource_2.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_1.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_1.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 7 s (elapsed).
Installed compiled interface for bsource_1.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_3.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_3.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 6 s (elapsed).
Installed compiled interface for bsource_3.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_4.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_4.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 7 s (elapsed).
Installed compiled interface for bsource_4.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_5.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_5.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 7 s (elapsed).
Installed compiled interface for bsource_5.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_6.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_6.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 16 s (elapsed).
Installed compiled interface for bsource_6.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_resmod_1.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_resmod_1.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 19 s (elapsed).
Installed compiled interface for bsource_resmod_1.
Opening directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB/bsource_7.input.ahdlcmi/ (775)
Created directory input.ahdlSimDB/bsource_7.input.ahdlcmi/Linux2.6.18-194.el5-64+gcc/ (775)
Compiling ahdlcmi module library.
Finished compilation in 26 s (elapsed).
Installed compiled interface for bsource_7.

Time for Elaboration: CPU = 2.44963 s, elapsed = 111.519 s (1m  51.5s).
Time accumulated: CPU = 3.13752 s, elapsed = 112.626 s (1m  52.6s).
Peak resident memory used = 110 Mbytes.

 

Parents

  •  Answering your questions out of order (makes it easier to explain).

    3. bsource is a "behavioral source" in spectre - it allows simple description of component values based on voltage and current relationships (amongst others), and is often used in model files to implement voltage dependent resistors, and so on (there are other ways, but the bsource allows arbitrary relationships rather than simple polynomial forms). They are implemented underneath using VerilogA.

    1. VerilogA code (including that for bsource) are compiled to C for speed, and then linked in with the simulator. Normally this is done incrementally, but in the case of ADE XL that wasn't happening.

    2. This is fixed in IC615 ISR4 (6.1.5.500.4). There is a workaround covered in Solution 11603330

    Andrew

Reply

  •  Answering your questions out of order (makes it easier to explain).

    3. bsource is a "behavioral source" in spectre - it allows simple description of component values based on voltage and current relationships (amongst others), and is often used in model files to implement voltage dependent resistors, and so on (there are other ways, but the bsource allows arbitrary relationships rather than simple polynomial forms). They are implemented underneath using VerilogA.

    1. VerilogA code (including that for bsource) are compiled to C for speed, and then linked in with the simulator. Normally this is done incrementally, but in the case of ADE XL that wasn't happening.

    2. This is fixed in IC615 ISR4 (6.1.5.500.4). There is a workaround covered in Solution 11603330

    Andrew

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