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how to pass array of parameters through CDF down to a verilogA code?

naderi

 Hello all,

 Is there any way to pass an array of parameters down to a verilogA code?

if I put following statement in a verilogA sub-circuit.

parameter real vdc[3:0] ={0,0,1,0};

Then {0, 0, 1, 0} appears in CDF parameters for vdc. However, spectre complains later during circuit read-in.The error message is :

 Error found by spectre during circuit read-in.
    ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{".

I realized if I enter the parameters within double-qoute as "{0, 0, 1, 0}" at CDF, then spectre will be happy and goes for simulation, but the results are incorrect.

 

I wonder if there is any solution?

Thanks,

Ali

Parents

  • Ali,

    You misunderstood. The VerilogA code needs to use {0,0,1,0} syntax, but in the CDF you'll need to define the default as [0 0 1 0] (no commas, although commas are tolerated at the moment - but you get a warning about them not being supported in the future). Also, when you instantiate the block, with a different value, you'd need to specify it with square brackets. To illustrate what I mean, here's some VerilogA:

     `include "disciplines.vams"

    module blah (op,ip);

    output op;
    input ip;
    electrical op,ip;

    parameter real vdc[3:0]={0,0,1,0};

    analog begin

       V(op) <+ vdc[2]*V(ip);

    end

    endmodule

    and here's the corresponding spectre netlist:

     //

    I1 (o1 i1) blah vdc=[2 2 2 2]

    v1 (i1 0) vsource type=sine freq=1M ampl=1

    ahdl_include "blah.va"
    tran tran stop=2u

     

Reply

  • Ali,

    You misunderstood. The VerilogA code needs to use {0,0,1,0} syntax, but in the CDF you'll need to define the default as [0 0 1 0] (no commas, although commas are tolerated at the moment - but you get a warning about them not being supported in the future). Also, when you instantiate the block, with a different value, you'd need to specify it with square brackets. To illustrate what I mean, here's some VerilogA:

     `include "disciplines.vams"

    module blah (op,ip);

    output op;
    input ip;
    electrical op,ip;

    parameter real vdc[3:0]={0,0,1,0};

    analog begin

       V(op) <+ vdc[2]*V(ip);

    end

    endmodule

    and here's the corresponding spectre netlist:

     //

    I1 (o1 i1) blah vdc=[2 2 2 2]

    v1 (i1 0) vsource type=sine freq=1M ampl=1

    ahdl_include "blah.va"
    tran tran stop=2u

     

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