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how to pass array of parameters through CDF down to a verilogA code?

naderi

 Hello all,

 Is there any way to pass an array of parameters down to a verilogA code?

if I put following statement in a verilogA sub-circuit.

parameter real vdc[3:0] ={0,0,1,0};

Then {0, 0, 1, 0} appears in CDF parameters for vdc. However, spectre complains later during circuit read-in.The error message is :

 Error found by spectre during circuit read-in.
    ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{".

I realized if I enter the parameters within double-qoute as "{0, 0, 1, 0}" at CDF, then spectre will be happy and goes for simulation, but the results are incorrect.

 

I wonder if there is any solution?

Thanks,

Ali

Parents

  • The above solution works when we actually pass parameters since the default parameters {1,2,3,4} are overridden by the passed parameters [1 2 3 4]. Generally I do not override parameters if I want to use the defaults. But due to this syntax problem I have to always pass parameters for the simulation to work.

    Is there a fix planed(to sync syntax of veriloga with spectre or viceversa)?

    Thanks and have a Wonderful day,

    Narasimhan Rajagopal

Reply

  • The above solution works when we actually pass parameters since the default parameters {1,2,3,4} are overridden by the passed parameters [1 2 3 4]. Generally I do not override parameters if I want to use the defaults. But due to this syntax problem I have to always pass parameters for the simulation to work.

    Is there a fix planed(to sync syntax of veriloga with spectre or viceversa)?

    Thanks and have a Wonderful day,

    Narasimhan Rajagopal

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