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how to pass array of parameters through CDF down to a verilogA code?

naderi over 13 years ago

Hello all,

Is there any way to pass an array of parameters down to a verilogA code?

if I put following statement in a verilogA sub-circuit.

parameter real vdc[3:0] ={0,0,1,0};

Then {0, 0, 1, 0} appears in CDF parameters for vdc. However, spectre complains later during circuit read-in.The error message is :

Error found by spectre during circuit read-in.
ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{".

I realized if I enter the parameters within double-qoute as "{0, 0, 1, 0}" at CDF, then spectre will be happy and goes for simulation, but the results are incorrect.

I wonder if there is any solution?

Thanks,

Ali

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Andrew Beckett over 9 years ago

Narasimhan,

There's not a need for spectre and veriloga to be aligned in terms of syntax, but there is a CCR for this to be handled correctly in the CDF - CCR 1094193. However, there is no plan to fix this - maybe that would change if more people asked for this via customer support.

Regards,

Andrew.
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Andrew Beckett over 9 years ago

Narasimhan,

There's not a need for spectre and veriloga to be aligned in terms of syntax, but there is a CCR for this to be handled correctly in the CDF - CCR 1094193. However, there is no plan to fix this - maybe that would change if more people asked for this via customer support.

Regards,

Andrew.
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nouning over 6 years ago in reply to Andrew Beckett

hi Andrew, I am facing the same issue: "ERROR (SFE-874): "input.scs" 1087: Unexpected block statement "{"." Has this issue been resolved yet? Can Spectre now handle VerilogA arrays such as {1,2,3,4}. Thank you.
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Andrew Beckett over 6 years ago in reply to nouning

Not sure when this was fixed, but a parameter such as in the example above now (in IC618 ISR3 - may have been this way for some time though) gets changed in the CDF to [0,0,1,0] (square brackets rather than curly brackets). This then works correctly because the netlist would contain the spectre vector syntax.

In earlier versions before this was done automatically, you can use Tools->CDF->Edit CDF, set the type to "Base" and pick the cell for which you have your VerilogA view. Change the vector parameter to have square brackets.

Then when instantiating the design in a schematic, on the create instance or edit properties form set the value with square brackets if you want something other than the default.

Regards,

Andrew.
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