proper usage of guard rings to clean substrate noise and minority carrier disturbances

Hi all, i am interested to know about your experiences with guard rings and also if you could advise me on certain design issues with guard rings. I have a mixed-signal design and I would like to seperate the noisy digital circuits from the sensitive analogue circuits. I mainly use p+ guard rings connected to it's dedicated pin. I have read in literature that p+ guard rings are more effective than n-well guard rings connected to vdd. also the distance of the p+ guard rings from the analogue circuits we wish to isolate is important. some papers suggest that n-well guard rings are not that effective at all at collecting minority carriers. i have area constraints on some parts of my design. I would like to get some advice on whether I should have n-well guard rings at all in my chip. 

my other question is regarding tapping ground/power connection for the circuits from the p+ guard ring. sometimes it's easy to connect the ground connections to the p+ guard rings around the circuits due to area and metal routing constraints. i have read in literature that this design methodology is acceptable if the peak current flowing through the transistors into the p+ guard ring is very small. Otherwise, tapping power from the guard ring is not acceptable.