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  3. How to set CDF to let both .subckt and .model work?

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How to set CDF to let both .subckt and .model work?

YG screen name
YG screen name over 13 years ago

Hi,

    I will create a mos pcell. There are two kinds of simulation model for the mos, one is subcircuit type(.subckt), the other is model type(.model). I want to know how to set CDF parameters for the mos cell in order to make the hspiceD simulator run correctly under both types.

    I know that the simulator parameter namePrefix is "X" for subcircuit type, and "M" for the model type. They are different. If I create only one cell, its parameter namePrefix is either "X" or "M". So I have to create two cells to adapt two types.  When I change the model type from one to the other, I have to modify the mos cell name in the schematic. If the amount of mos is large, it will not be a good idea.

   Is there any way supporting the two types of model to create only one cell to simulate the mos?

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  • Andrew Beckett
    Andrew Beckett over 13 years ago

    One idea is to use view-specific CDF. Create a copy of the stop view for the device (hspiceD normally - I called it "hspiceD_subckt").

    Then define the view-specific CDF (no GUI for this; you have to use SKILL):

    lib="gpdk090"
    cell="nmos1v"
    stopView="hspiceD_subckt"
    almSetNamePrefix(lib cell "X" ?view stopView)
    ; copy the terminal list and parameter list from the standard CDF simInfo:
    almSetTerminalList(lib cell almGetTerminalList(lib cell ?tool "hspiceD") ?view stopView)
    almSetParameterList(lib cell almGetParameterList(lib cell ?tool "hspiceD") ?view stopView)
    ;; may need some of the other alm functions - see the documentation

    Then when you use the device you can either use the hierarchy editor to define "hspiceD_subckt" as another stopping view, and pick the instances that you want to be netlisted as instances by setting their view to use to be "hspiceD_subckt". Or in ADE (if you're not using a config) you can simply alter the switch list order (Setup->Environment - put "hspiceD_subckt" before "hspiceD", and add "hspiceD_subckt" to the stop list).

    I'm assuming here that your default simInfo will netlist as "M" prefix, and the code above will define the new view as netlisting as "X".

    If you are using spectre as the simulator, you don't have to do any of this messing around, since it does not use the instance name to determine the component type - it doesn't matter whether you are instantiating a built-in primitive, a model, a VerilogA module or a subckt - they all look the same as far as the instance is concerned.

    Regards,

    Andrew.

     

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  • Andrew Beckett
    Andrew Beckett over 13 years ago

    One idea is to use view-specific CDF. Create a copy of the stop view for the device (hspiceD normally - I called it "hspiceD_subckt").

    Then define the view-specific CDF (no GUI for this; you have to use SKILL):

    lib="gpdk090"
    cell="nmos1v"
    stopView="hspiceD_subckt"
    almSetNamePrefix(lib cell "X" ?view stopView)
    ; copy the terminal list and parameter list from the standard CDF simInfo:
    almSetTerminalList(lib cell almGetTerminalList(lib cell ?tool "hspiceD") ?view stopView)
    almSetParameterList(lib cell almGetParameterList(lib cell ?tool "hspiceD") ?view stopView)
    ;; may need some of the other alm functions - see the documentation

    Then when you use the device you can either use the hierarchy editor to define "hspiceD_subckt" as another stopping view, and pick the instances that you want to be netlisted as instances by setting their view to use to be "hspiceD_subckt". Or in ADE (if you're not using a config) you can simply alter the switch list order (Setup->Environment - put "hspiceD_subckt" before "hspiceD", and add "hspiceD_subckt" to the stop list).

    I'm assuming here that your default simInfo will netlist as "M" prefix, and the code above will define the new view as netlisting as "X".

    If you are using spectre as the simulator, you don't have to do any of this messing around, since it does not use the instance name to determine the component type - it doesn't matter whether you are instantiating a built-in primitive, a model, a VerilogA module or a subckt - they all look the same as far as the instance is concerned.

    Regards,

    Andrew.

     

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