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How to run Assura LVS with vldb and cdl.

armthy

 Hello Community,

 I am working on a ibm pdk kit. My design block has cells coming from the pdk and also from the stdcell library from ibm.

The standard cell cadence library has only a symbol view for the cells(I did a  stream in and now also have a layout view) . There is a cdl for all the cells but no schematic views.

I was hoping that I could point to the cdl file as part of "schematic netlisting options form", in assura lvs gui, for the stdcell library cells used in the design.

So I was hoping to run Schematic Design Source-->DFII so all the other primitves that have all needed views in cadence can be used as is. Howvever, this does not seem to work.

So my questions is, How to run Assura LVS with vldb and use cdl netlist for the stdcell library.

Thanks for any help you can provide.

  • That ought to work. What versions are you using (of Assura, and of Virtuoso/icfb)? (please give subversions - what does:

    icfb -W (or virtuoso -W if using IC61X)
    assura -W

    output?

    Regards,

    Andrew.

  •  Hi Andrew,

    Thanks for replying to my issue. The fets from the cdl comes out unbound. The exact message is "nfet on schematic is unbound to any layout device". For example if I have a inverter created thru the stdCellLibrary and another inventer by putting together fets from pdk. The LVS extracts the fets from the pdk correctly and not the one thru stdCellLibrary(they are the exact same device). Please let me know if that make sense.

    Versions are

    IC6.1.5.500.7

    assura 4.1_USR2

  • The versions you're using are pretty up to date.

    You'll probably need to update the binding rule (bind.rul) file to tell it how to bind the CDL netlist devices to the extracted devices. You should already have a bind rule file in the existing setup (I expect), but more detail can be found in the Assura documentation.

    Effectively this is something that tells it how a particular netlist device corresponds to a particular layout extracted device (amongst other things). The name of the device may be different in the CDL from how it gets treated from the schematic (which is probably using information from the auLvs simInfo in the CDF to describe the device).

    Andrew.

  •  Hi Andrew,

     

    Thanks for the recommendation.  I do see that in the bind file that there is a mapping of the said fets in both schematic and layout.

    I am contacting ibm as I think they shld be able to provide guidance as it their libs. Thanks again for your suggestions and help on this issue.

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