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Query regarding LVS extraction

SSSJ
Hi, I have placed the pcells i.e resistors and launched layout-xl from schematic, and it has cleared the lvs. After the LVS pass when I check the netlist the resistance value of schematic / layout are having a difference of 1.34. For ex: In schematic - r = 57.23, In layout - r = 59.011 Why it is giving such a big difference, which is supposed to be same or does it depend on any tolerance value ? Thanks in advance

  • There are many reasons why this could be. It could be that the verification is done base on the size rather than the value, and that there is a failure to run a callback on the schematic. Or it may be that there's a large tolerance in the rules you're using. Very hard to tell based on the limited information you gave. It's probably a good question for whoever provided you with the design kit and LVS/extraction rules. You've not mentioned what technology you're using, what tools or versions you're using, so anyone familiar with those technologies who subscribes to this forum won't be able to know if they might be able to give you some more specific advice.

    Regards,

    Andrew.

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