VHDLIN producing symbols, not schematics

Hello.

 I have some existing VHDL designs which I am trying to import into Cadence (5.14) using the vhdlin tool.  I can import the designs, however instead of geting a schematic as I expect, I get an (automatically generated) entity file and a symbol.  The architecture of the design seems to be ignored.  Here's what I've tried so far to remedy the situation.

 1) Ensure component binding in the vhdl file.  Just to be sure there's no ambiguity with the default binding or which architectures to be instanciated.

 2) Softinclude the cds.lib files from leapfrog and inca, to make sure no reference libraries are missing.

 3) Used ncvhdl to compile my designs.  It works fine, but I get an entity (which is just a symbolic link to my source code) and the architecture in vhdl (again a symbolic link to the original source).  It seems my vhdl code is error-free.

4) I get a glibc error stating: "double free or corruption", which seems to be a memory allocation issue with the OS (RHEL), which I doubt would allow the symbol view to be created instead of the schematic view.

 Are there other things to try?  Other ways to diagnose what the problem is?  The VHDLIN manual has a section on limitations which I've been careful to follow, and yet I still seem to be having the same problems.  VHDLIN defaults to the symbol even though as far as I can tell, the import function should work.