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" *Error* plus: can't handle (nil + nil) " during netlisting in icfb

yayla

Hi,

 When I am running simulation with Spectre under ADE, I am getting many errors saying that "*Error* plus: can't handle (nil + nil)" during netlisting and I couldn't start simulation. Before these error messages, I am getting "Terminal "xx" doesn't exist in cell-view "xx" "schematic"". In our project, we are using SOS to keep revision history for schematic and symbol. When I update the workarea, I use SOS and there are 3 options under it: Update(changed cellviews and files existing in workare only), Update(Get new Cells and vies into workarea) and Update(Force all). I started to see these problem after I have updated with Force All option. However, I am not sure whether this is real issue.

As I said before, I am getting this netlisting error sometimes but when netlisting is succesful, simulation(transient,pss etc) runs much fasterthan before and all outputs are zero.

 

Do you have any idea what might be reason?

Thanks,

 Mustafa

  • The terminal message is quite likely due to there being either a mismatch between the symbol and the schematic, or more likely between the termOrder in the spectre simInfo in the CDF for that block and the symbol/schematic. If it's the latter, it's just a warning and should be benign.

    The plus: can't handle (nil + nil) during netlist - that's harder to diagnose without working out where it is coming from (it's an uncaught error somewhere low in some code - maybe something in the PDK or it maybe in the Cadence code somewhere).

    I would suggest that you log a service request with customer support for this.

    Regards,

    Andrew.

  • Thanks Andrew. As you mentioned, CDF port names are not matched to schematic&symbol. I need to update prop.xx file  to solve this issue. 

    For the error, I will submit a request. 

    Thanks,

     yayla

  • Quick update for other people:

    I have tried to netlist just one transistor but even I couldn't so we checked attached tech files but there was no. Hence, we have attached the required tech files. It seems that problem is solved.

     Thanks,

     yayla

  • Yayla,

    Glad you sorted it out. Note that in general this isn't necessary, so it's obviously something to do with the specific PDK you're using.

    Regards,

    Andrew.

  •  Hi Andrew,

    I don't want to open a new thread since it is still related to this topic. I am getting many warning messages when I try to generate netlist in icfb which states that "xxxx yyy symbol" updated since last schematic save. I am getting this warning message when I change design variable in ADE or change the signal to be plot in Setting Output Window ADE. As I mentioned before, we are using SOS to keep revision history. I have checked-in schematic "yyy" but stil I have the probem.

     Thanks,

     yayla

  • Yayla,

    That message would normally suggest that you should do a check-and-save of the containing schematic. If the symbol has changed, anything that uses it potentially has incorrect connectivity. Of course, the changes may be purely cosmetic, but it's a warning that there is potentially a problem. 

    I wouldn't expect to see that when you change a design variable - only when it is netlisting. So not sure why that would be. Anyway it's nothing to do with the schematic for yyy, but the parent of yyy...

    Andrew.

  • Hi, I'm using TSMC 65nm in Cadence for RF design in 60 GHz. I have two questions:

    1- in "spiral_sym_mu_z_9m" the third pad should be connected to ground?

    2- Does this inductor work for 60 GHz? becuase in inductor finder it says that it works up to 20Ghz.

    Thanks 

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