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Time Delay in VCVS & Delay Block in Spectre (Cadence 5) no influence

tstoll
Hi all -
I have in Cadence 6 a testbench where I delay an output transient signal using a VCVS with the time delay option.
That works quite well.
In our Cadence 5 setup I implemented the same testbench, also using the VCVS as delay element.. But here the time delay setting shows NO influence.
Any hint on that?

Best regards,
Thomas   
  • tstoll

    hi -

    I found following link on the web:

     http://www.docin.com/p-85475985.html?bsh_platform=renren

     

    Solution would be to  hand map this statement to an equivalent spectre delay element:

     

    e1 (n1 n2 n1 0) delay td=td0

     

    BUT HOW TO DO THAT?  Where shall I add that?

     

    Best regards,

    Thomas 

  • Andrew Beckett

    Thomas,

    The limiting factor is if you use spectre from IC5141. This is not a good idea, since it hasn't been updated since 2008, and even then between 2004 and 2008 there were only limited fixed. As you may know, spectre was moved from being shipped in the IC stream to be part of the MMSIM stream, and there have been numerous releases of MMSIM in the meantime.

    You should be able to use whichever version of MMSIM that you're using with IC61X with IC5141 too - just make sure that <MMSIMinstDir>/tools/bin is earlier in your UNIX path variable than <ICinstDir>/tools/dfII/bin and <ICinstDir>/tools/bin . Then it should work fine (I checked). Looking at spectre from IC5141 itself though, it did not support the td parameter.

    The workaround would be to place an instance of the delay component from analogLib - no need to hand code anything.

    BTW, somebody is breaking their license agreement by placing those documents on the web...

    Regards,

    Andrew.

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