Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 13413
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

pcell problem

Stefan Bormann

 Hi,

I have the following question.

I updated our pdk (tsmc process) with some addons for rf devices and minor techlib tweaks.

We have some special capacitors  (crtmom). The pcell for this is working good, but

if I open an old layout with pcells from before the chance I miss some layers (VIA2 and MET2).

The strange things is this:

In the same layout I have both types of the layouts (created by the pcell before and after the change).

1) copying/editing the new one all is correct, also if I insert it from the techlib as a new part.

2) copying/editing the old oneit still have the old layout (without MET2 / VIA2) inserting a part again from the techlib (the same cell as in step1) it comes with the wrong layout (without MET2/VIA2)

 copying cell to another cell with different name doesn't help.

that means replacing  hierachical is not working.

 

Any ideas how I can virtuoso force to use the correct pcell?

Thanks in advance.

-Stefan

  • Stefan Bormann

     Hi,

    I found the error,

    I had to rerun a tsmc script on the pdk library to generate the pcells.

    So the problem was the pcell.

    Now it is working as it should.

    Regards

    -Stefan

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.