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pcell problem

Stefan Bormann

 Hi,

I have the following question.

I updated our pdk (tsmc process) with some addons for rf devices and minor techlib tweaks.

We have some special capacitors  (crtmom). The pcell for this is working good, but

if I open an old layout with pcells from before the chance I miss some layers (VIA2 and MET2).

The strange things is this:

In the same layout I have both types of the layouts (created by the pcell before and after the change).

1) copying/editing the new one all is correct, also if I insert it from the techlib as a new part.

2) copying/editing the old oneit still have the old layout (without MET2 / VIA2) inserting a part again from the techlib (the same cell as in step1) it comes with the wrong layout (without MET2/VIA2)

 copying cell to another cell with different name doesn't help.

that means replacing  hierachical is not working.

 

Any ideas how I can virtuoso force to use the correct pcell?

Thanks in advance.

-Stefan

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