set design variables in ADE XL

 Hi,

I am still dealing with the problem I discribed earlier on but made some progress.

By looking into the netlist.vams and cds_globals.vams I figured out the following: 

Each variable I add is listed in the cds_globals.vams  for example when using the vsource in a schematic and I assign Phase to  Initial phase for Sinusoid the entry in the cds_globals.vams looks somewhat like this:

// Verilog-AMS cds_globals module for top-level cell:
//    test/testbench_PLL2.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
   electrical \gnd! ;
   ground \gnd! ;

// Design Variables
   dynamicparam real Phase = -90;
 

endmodule

 

And the  associated netlist.vams looks like this.

// AMS netlist generated by the OSS based AMS netlister
// IC subversion:  IC6.1.4.500.6
// IUS version: 09.20-s022
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: seth3685 Pid: 22606
// Design library name: test
// Design cell name: testbench_PLL2
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// Library - test, Cell - testbench_PLL2, View - schematic
// LAST TIME SAVED: Apr 23 08:29:20 2012
// NETLIST TIME: Apr 23 08:29:27 2012
`timescale 1ns / 1ps

(* cds_ams_schematic *)
module testbench_PLL2 ();


vsource #(.mag(1), .type("sine"), .sinephase(cds_globals.Phase),
    .freq(150K)) V0 (Sig_in, cds_globals.\gnd! );

 endmodule 

But when I use my verilog ams models in a schematic (e.g the VCO2 ) and I assign Ampl to the output amplitude of the VCO signal the netlist.vams looks different in one point. It looks like this:

VCO2 #( .Fmin(97.48k), .Fmax(102.52k), .ampl("Ampl"), .Vmax(6), .Vmin(0)
    , .Fo(100K) ) I4 ( .out(VCO_out), .in(TP_out));

So has anyone an idea how to solve this? I can I get ade xl to wirte  .ampl(cds_globals.Ampl) instead of .ampl("Ampl")?

Looking forward to your replies 

 Hi,

okay problem is solved. For the sake of completness I would like to tell you , how I have managed to get around this problem:

1) open the CDF Tool 

2) Open the corresponding module: scope: "cell " in the  CDF layer "base"

3) enable " parse as number" option 

4) Open ADE XL and add the Design Varibles you have included in your  Verilog AMS Code

And that should do the job.

Bye Bye 

Ps: This is how the cdfDump file looks like now: 

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  cdfCreateParam( cdfId
        ?name           "Fo"
        ?prompt         "Fo"
        ?defValue       "4.5e+07"
        ?type           "string"
        ?display        "artParameterInToolDisplay('Fo)"
        ?parseAsNumber  "yes"
        ?parseAsCEL     "yes"

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