Hello, I am experiencing quite a few problems when trying to include a VHDL file into a mixed signal testbench to verify its functionalities. The testbench is created (config + schematic), the vhdl file was imported with "VHDL Import" (following Cadence Help Docs...). The tool creates 3 cell views: entity, rtl and symbol. After that I set the binding view in Hierarchy Editor to "entity" and try to run the simulation (note that "entity" view has only the entity part of VHDL code, and "rtl" view has the actual behavioural code).
I get an error message stating: "ncelab: *F,CUIVEN: Illegal view named entity specified for binding in sil180_adc_spi.el_spi_static:entity."
Ok, trying to solve this I create a "vhdl" cellview for the same block, containing the whole VDHL code (entity + rtl). This time, when I modify this new "vhdl" view, the tool automatically updates the other two views ("entity" and "rtl"). Going back to Hierarchy Editor I set the current view of the block to "vhdl" and try to run the sim again.
This time I get the following errors:
ncelab: *W,CUNOUN: Cannot find any unit under sil180_adc_spi.el_spi_static:vhdl in the design libraries.ncelab: *E,DLCSMD: Dependent checksum entity SIL180_ADC_SPI.EL_SPI_STATIC (AST) doesn't match with the checksum that's in the header of: architecture SIL180_ADC_SPI.EL_SPI_STATIC:RTL (AST).
I really tried to find out WHAT this error means. Can anyone give a hand here?
Thanks in advance.
I am facing the identical problem. I wonder if you could somehow figure it out.
I'd really appreciate it if you could help.
Did you use git as version control program?