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Assura LVS error (cell expanded), need help debugging the error !!

SivaChaitanya

hi,

I generated a LVS report for a design i'm working on using assura which had an error as cells expanded

the summary of the error report is shown below

*******************************************************************************
****** ff schematic ff  <vs>  ff layout ff
*******************************************************************************
                                                                                                                                                                                                                           
Pre-expand Statistics                     
======================                          Original      
Cell/Device                               schematic  layout
(buffer schematic buffer, buffer) Cell            2       2
(inverter schematic inverter, inv...) Cell        2       2
(tris-state schematic tri-state, ...) Cell        4       4
(N_10_SP) MOS                                     0      14*
                                             ------  ------
Total                                             8      22

Filter Statistics
=================                               Original            Filtered
Cell/Device                               schematic  layout   schematic  layout
(N_10_SP) MOS                                    14      14          14      14
(P_10_SP) MOS                                    14      14          14      14

Reduce Statistics
=================                               Filtered             Reduced
Cell/Device                               schematic  layout   schematic  layout
(N_10_SP) MOS                                    14      14           6       6
(P_10_SP) MOS                                    14      14           6       6
(N_10_SP:SerMos2#1) MosBlk                        -       -           4       4
(P_10_SP:SerMos2#1) MosBlk                        -       -           4       4

Match Statistics
================                                  Total             Unmatched
Cell/Device                               schematic  layout   schematic  layout
(N_10_SP) MOS                                     6       6           0       0
(P_10_SP) MOS                                     6       6           0       0
(N_10_SP:SerMos2#1) MosBlk                        4       4           0       0
(P_10_SP:SerMos2#1) MosBlk                        4       4           0       0
                                             ------  ------      ------  ------
Total                                            20      20           0       0

Match Statistics for Nets                        12      16           0       4

===========================================================================[ff]
====== Unbound Pin ============================================================
===============================================================================

S nq

===========================================================================[ff]
====== Unmatched Internal Nets ================================================
===============================================================================

L ?avC5_3
L ?avC5_6
L ?avC6
L ?avC5_11

===========================================================================[ff]
====== Bad Matched Nets (don't really match) ==================================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 1)
Schematic Net:  net30
S       1   of P_10_SP {D S}
S      *1   of P_10_SP G
S       1   of N_10_SP {D S}
S      *1   of N_10_SP G
S      *2   of N_10_SP:SerMos2#1 {IN1 IN2}
S      *2   of P_10_SP:SerMos2#1 {IN1 IN2}

Layout Net:  avC6_3
L       1   of P_10_SP {D S}
L       1   of N_10_SP {D S}

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 2)
Schematic Net:  net29
S       1   of P_10_SP {D S}
S       1   of N_10_SP {D S}
S       2   of N_10_SP:SerMos2#1 {IN1 IN2}
S       2   of P_10_SP:SerMos2#1 {IN1 IN2}

Layout Net:  avC8
L       1   of P_10_SP {D S}
L       1   of N_10_SP {D S}
L      *1   of N_10_SP:SerMos2#1 {IN1 IN2}
L       2   of P_10_SP:SerMos2#1 {IN1 IN2}

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 3)
Schematic Net:  nq
S       1   of P_10_SP {D S}
S      *1   of P_10_SP G
S       1   of N_10_SP {D S}
S      *1   of N_10_SP G

Layout Net:  avC6_6
L       1   of P_10_SP {D S}
L       1   of N_10_SP {D S}

===========================================================================[ff]
====== Suggested Terminal Rewire ==============================================
===============================================================================

In the layout, terminal 'IN1' of instance I##34 probably should connect to net
avC6_3 instead of net avC6.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'IN1' of instance I##29 probably should connect to net
avC6_3 instead of net avC6.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'IN1' of instance I##35 probably should connect to net
avC6_3 instead of net avC6.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'IN1' of instance I##32 probably should connect to net
avC6_3 instead of net avC6.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'G' of instance avD1824_9 probably should connect to
net avC6_3 instead of net avC5_3.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'G' of instance |I0/|I1/avD1842_1 probably should
connect to net avC6_3 instead of net avC5_3.
This makes a better match between layout net avC6_3 and schematic net net30.

In the layout, terminal 'G' of instance avD1824_7 probably should connect to
net avC6_6 instead of net avC5_6.
This makes a better match between layout net avC6_6 and schematic net nq.

In the layout, terminal 'G' of instance |I7/|I1/avD1842_1 probably should
connect to net avC6_6 instead of net avC5_6.
This makes a better match between layout net avC6_6 and schematic net nq.


===========================================================================[ff]
====== Open Internal Nets =====================================================
===============================================================================

These layout nets should connect together:
L        avC5_3
L        avC8
L        avC5_11

These layout nets should connect together:
L        avC6_3
L        avC6

===========================================================================[ff]
====== Problem Schematic Nets (no exact match in layout) ======================
===============================================================================
S
S ?nq
S       1   of P_10_SP {D S}
S       1   of P_10_SP G
S       1   of N_10_SP {D S}
S       1   of N_10_SP G
S
S ?net29
S       1   of P_10_SP {D S}
S       1   of N_10_SP {D S}
S       2   of N_10_SP:SerMos2#1 {IN1 IN2}
S       2   of P_10_SP:SerMos2#1 {IN1 IN2}
S
S ?net30
S       1   of P_10_SP {D S}
S       1   of P_10_SP G
S       1   of N_10_SP {D S}
S       1   of N_10_SP G
S       2   of N_10_SP:SerMos2#1 {IN1 IN2}
S       2   of P_10_SP:SerMos2#1 {IN1 IN2}

===========================================================================[ff]
====== Problem Layout Nets (no exact match in schematic) ======================
===============================================================================
L
L ?avC5_11
L       1   of N_10_SP:SerMos2#1 {IN1 IN2}
L
L ?avC6_3 ?avC6_6
L (total 2) with:
L       1   of P_10_SP {D S}
L       1   of N_10_SP {D S}
L
L ?avC5_3 ?avC5_6
L (total 2) with:
L       1   of P_10_SP G
L       1   of N_10_SP G
L
L ?avC6
L       2   of N_10_SP:SerMos2#1 {IN1 IN2}
L       2   of P_10_SP:SerMos2#1 {IN1 IN2}
L
L ?avC8
L       1   of P_10_SP {D S}
L       1   of N_10_SP {D S}
L       1   of N_10_SP:SerMos2#1 {IN1 IN2}
L       2   of P_10_SP:SerMos2#1 {IN1 IN2}

===========================================================================[ff]
====== Matched Instances with Bad Net Connections =============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 1)
Schematic Instance: I7/I1/PM0  P_10_SP
Layout Instance:    |I7/|I1/avD1842_1  P_10_SP

Pin        SchNet                      : LayNet
---        ------                      : ------
G          nq                          : ?avC5_6

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 2)
Schematic Instance: I7/I1/PM1  N_10_SP
Layout Instance:    avD1824_7  N_10_SP

Pin        SchNet                      : LayNet
---        ------                      : ------
G          nq                          : ?avC5_6

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 3)
Schematic Instance: I0/I1/PM0  P_10_SP
Layout Instance:    |I0/|I1/avD1842_1  P_10_SP

Pin        SchNet                      : LayNet
---        ------                      : ------
G          net30                       : ?avC5_3

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 4)
Schematic Instance: I0/I1/PM1  N_10_SP
Layout Instance:    avD1824_9  N_10_SP

Pin        SchNet                      : LayNet
---        ------                      : ------
G          net30                       : ?avC5_3

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 5)
Schematic Instance: I##29  N_10_SP:SerMos2#1
Layout Instance:    I##32  N_10_SP:SerMos2#1

Pin        SchNet                      : LayNet
---        ------                      : ------
IN1        net30                       : ?avC6
IN2        net6                        : net6

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 6)
Schematic Instance: I##31  N_10_SP:SerMos2#1
Layout Instance:    I##31  N_10_SP:SerMos2#1

Pin        SchNet                      : LayNet
---        ------                      : ------
IN1        net29                       : ?avC5_11
IN2        net18                       : net18

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 7)
Schematic Instance: I##32  P_10_SP:SerMos2#1
Layout Instance:    I##35  P_10_SP:SerMos2#1

Pin        SchNet                      : LayNet
---        ------                      : ------
IN1        net30                       : ?avC6
IN2        net18                       : net18

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 8)
Schematic Instance: I##33  N_10_SP:SerMos2#1
Layout Instance:    I##29  N_10_SP:SerMos2#1

Pin        SchNet                      : LayNet
---        ------                      : ------
IN1        net30                       : ?avC6
IN2        D                           : D

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 9)
Schematic Instance: I##36  P_10_SP:SerMos2#1
Layout Instance:    I##34  P_10_SP:SerMos2#1

Pin        SchNet                      : LayNet
---        ------                      : ------
IN1        net30                       : ?avC6
IN2        net18                       : net18

===========================================================================[ff]
====== Summary of Errors ======================================================
===============================================================================

Schematic  Layout     Error Type
---------  ------     ----------
 3          3         Bad Matched Nets
 -          8         Suggested Terminal Rewire
 -          4         Unmatched Internal Nets
 -          2         Open Internal Nets
 9          9         Matched Instances with Bad Net Connections
 1          -         Unbound Pin

could you please help me debug the problem ?

thanks

Siva

  • Issue is solved now, there has been a short in my metal layers of my layout which caused this problem and from the forums i found that heirachically placing the transistor might solve this issue as well. Hope the information helps someone 

     

    Siva 

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