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verilog-a - model ac biasing

soathana

Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre.

 kind regards,

Sotiris

 

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  • Sotiris,

    It's not that clear to me what you're trying to do. What do you mean by "probe simulator as to the biasing conditions of a model..."? What does that actually mean?

    Maybe you are talking about turning on the saving of internal variables - if so, this can be achieved by turning on saveahdlvars in the Save All form in ADE (or adding "mysaveopts options saveahdlvars=all" or "mysaveops options saveahdlvars=allwithnodes" to your netlist before simulating it).

    Regards,

    Andrew.

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  • Sotiris,

    It's not that clear to me what you're trying to do. What do you mean by "probe simulator as to the biasing conditions of a model..."? What does that actually mean?

    Maybe you are talking about turning on the saving of internal variables - if so, this can be achieved by turning on saveahdlvars in the Save All form in ADE (or adding "mysaveopts options saveahdlvars=all" or "mysaveops options saveahdlvars=allwithnodes" to your netlist before simulating it).

    Regards,

    Andrew.

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