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verilog-a - model ac biasing

soathana
soathana over 13 years ago

Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre.

 kind regards,

Sotiris

 

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  • soathana
    soathana over 13 years ago

    Andrew,

    Sorry for the bad description. What i would like to do is that depending for example on whether a node in my model has an ac source attached to it or a dc source attached to it, affect its behaviour. There are options for example for requesting $time $temperature and analysis("type")  from spectre .Is there a way to probe from the model the spice netlist. i.e. something like if net#=vsin do something if net#=vdc do something else? If not could this be done automatically through SKILL/ other scripted way and redirect information inside verilogA somehow?

    kind regards,

    Sotiris

     

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  • soathana
    soathana over 13 years ago

    Andrew,

    Sorry for the bad description. What i would like to do is that depending for example on whether a node in my model has an ac source attached to it or a dc source attached to it, affect its behaviour. There are options for example for requesting $time $temperature and analysis("type")  from spectre .Is there a way to probe from the model the spice netlist. i.e. something like if net#=vsin do something if net#=vdc do something else? If not could this be done automatically through SKILL/ other scripted way and redirect information inside verilogA somehow?

    kind regards,

    Sotiris

     

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