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verilog-a - model ac biasing

soathana

Is there a way to probe simulator as to the biasing conditions of a model implemented in verilog-a ? If not is this possible through verilog-a, via some kind of monitoring scheme or someone must go into spice netlist level? The simulator used is spectre.

 kind regards,

Sotiris

 

Parents

  •  Andrew,

    Sorry for the late responce. I was on vacations. The thing is that I am impementing some aging effects on BSIM4, and they are partially dependent on past biasing conditions of the circuit. Anyways probably I think I will try with SKILL.

    cheers,

    Sotiris

Reply

  •  Andrew,

    Sorry for the late responce. I was on vacations. The thing is that I am impementing some aging effects on BSIM4, and they are partially dependent on past biasing conditions of the circuit. Anyways probably I think I will try with SKILL.

    cheers,

    Sotiris

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