• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Transient simulation taking too much memory

Stats

  • Locked Locked
  • Replies 20
  • Subscribers 126
  • Views 24535
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Transient simulation taking too much memory

vshssvs7
vshssvs7 over 13 years ago

Sir,

I have to run a transient simulation of a transistor-level Charge Pump PLL. I have noticed that it is taking too much memory. icfb got shutdown by itself with this message at the terminal:

ERROR: Unable to allocate memory for transition file slice variable transition index level (read).

The simulation was not complete and it shutdown in between. The size of tran.tran.trn is around 40 GB.

Note that I have already done this: In Analog Design Environment, Outputs -> Save All, I have checked "selected" option in "select signals to output (save)" and Outputs -> to be saved -> select on schematic and selected few nets that I wanted to save

But even after doing the above, it is still saving every net (because I'm able to plot those nets) which is the reason for such a huge tran.tran.trn file. What more should I do to stop it from saving every net? (and only save the nets that I select) 

 

  • Cancel
Parents
  • vshssvs7
    vshssvs7 over 13 years ago

    Sorry sir, I posted that message before I saw your reply.

    I (re)started the simulation again yesterday itself with strobe period as 10n in transient analysis options to reduce the data. The simulation is going on currently. I'm not sure what I checked/unchecked in 'save device currents' line when the problem occured (first time simulation). But currently input.scs file is as follows:

    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27.0 \

        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \

        dochecklimit=yes checklimitdest=psf 

    tranCheckLimit checklimit checkallasserts=yes severity=none

    tran tran stop=30u errpreset=moderate write="spectre.ic" \

        writefinal="spectre.fc" annotate=status save=selected strobeperiod=10n \

        maxiters=5 

    finalTimeOP info what=oppoint where=rawfile

    designParamVals info what=parameters where=rawfile

    primitives info what=primitives where=rawfile

    subckts info what=subckts  where=rawfile

    asserts info what=assert  where=rawfile

    save vctl 

    saveOptions options save=none pwr=none useprobes=no

    ahdl_include "/cad/tools/cadencetools/IC5141_USR6/tools/dfII/samples/artist/ahdlLib/vco/veriloga/veriloga.va" 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • vshssvs7
    vshssvs7 over 13 years ago

    Sorry sir, I posted that message before I saw your reply.

    I (re)started the simulation again yesterday itself with strobe period as 10n in transient analysis options to reduce the data. The simulation is going on currently. I'm not sure what I checked/unchecked in 'save device currents' line when the problem occured (first time simulation). But currently input.scs file is as follows:

    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27.0 \

        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \

        dochecklimit=yes checklimitdest=psf 

    tranCheckLimit checklimit checkallasserts=yes severity=none

    tran tran stop=30u errpreset=moderate write="spectre.ic" \

        writefinal="spectre.fc" annotate=status save=selected strobeperiod=10n \

        maxiters=5 

    finalTimeOP info what=oppoint where=rawfile

    designParamVals info what=parameters where=rawfile

    primitives info what=primitives where=rawfile

    subckts info what=subckts  where=rawfile

    asserts info what=assert  where=rawfile

    save vctl 

    saveOptions options save=none pwr=none useprobes=no

    ahdl_include "/cad/tools/cadencetools/IC5141_USR6/tools/dfII/samples/artist/ahdlLib/vco/veriloga/veriloga.va" 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information