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Cannot pass parameters from virtuoso sch. into Verilog module

Pavel47

 Hello,

 I've met problem while passing parameter value, specified on the schematic.

Here is Verilog module:

module Pixel_v0 (input Din, CLK, output Dout );
   parameter SEED = 33;
   integer INTSEED=SEED;
   reg [15:0] DATA;
   assign Dout = DATA[15];

//   initial DATA = $random(INTSEED);
   initial DATA = INTSEED;
  

   generate
      genvar  i;
      for (i = 0; i < 15; i=i+1) begin: DFF
     if (i==0)
       always @(posedge CLK)
         DATA[i] <= Din;
     always @(posedge CLK)
       DATA[i+1] <= DATA[i];
      end
   endgenerate

endmodule

On the picture on attachment I shoved concrned instance (with parameter value = 15) and signal waveform. As you can constate, the initial DATA value is 33 (as spicified inside of verilog module), but not 15 (as sppecified in schematic).

Where is a problem.

Thanks in advance.

Pavel. 

Parents

  • Andrew,

    I've found this info inside of Virtuoso NC Verilog Environment User Guide:

    CDF properties can be used by either creating a Verilog hierprop property or by using hnlVerilogCDFdefparamList parameter.
    If an instance has CDF parameters, the user does not need to create a Verilog hierprop property to ask the Verilog netlister to print out CDF properties by defparam statement. But the user does need to create a hnlVerilogCDFdefparamList property on the switched master of the instance cell.
    property name: hnlVerilogCDFdefparamList
    property type: list type
    property value(example): (“Asim” “Lsim” “l” “w” “Wsim”)
    The Verilog formatter looks first at the instance Verilog hierprop properties and prints out those properties. Then, the formatter looks at the switched master of instance to determine whether property hnlVerilogCDFdefparamList exist.

    But I didn't find what is switched master ?

    I've searched everywhere - cdnshelp, google, etc. - no definition at all.

    Regards.

    Pavel.

Reply

  • Andrew,

    I've found this info inside of Virtuoso NC Verilog Environment User Guide:

    CDF properties can be used by either creating a Verilog hierprop property or by using hnlVerilogCDFdefparamList parameter.
    If an instance has CDF parameters, the user does not need to create a Verilog hierprop property to ask the Verilog netlister to print out CDF properties by defparam statement. But the user does need to create a hnlVerilogCDFdefparamList property on the switched master of the instance cell.
    property name: hnlVerilogCDFdefparamList
    property type: list type
    property value(example): (“Asim” “Lsim” “l” “w” “Wsim”)
    The Verilog formatter looks first at the instance Verilog hierprop properties and prints out those properties. Then, the formatter looks at the switched master of instance to determine whether property hnlVerilogCDFdefparamList exist.

    But I didn't find what is switched master ?

    I've searched everywhere - cdnshelp, google, etc. - no definition at all.

    Regards.

    Pavel.

Children
No Data

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