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Cannot pass parameters from virtuoso sch. into Verilog module

Pavel47

 Hello,

 I've met problem while passing parameter value, specified on the schematic.

Here is Verilog module:

module Pixel_v0 (input Din, CLK, output Dout );
   parameter SEED = 33;
   integer INTSEED=SEED;
   reg [15:0] DATA;
   assign Dout = DATA[15];

//   initial DATA = $random(INTSEED);
   initial DATA = INTSEED;
  

   generate
      genvar  i;
      for (i = 0; i < 15; i=i+1) begin: DFF
     if (i==0)
       always @(posedge CLK)
         DATA[i] <= Din;
     always @(posedge CLK)
       DATA[i+1] <= DATA[i];
      end
   endgenerate

endmodule

On the picture on attachment I shoved concrned instance (with parameter value = 15) and signal waveform. As you can constate, the initial DATA value is 33 (as spicified inside of verilog module), but not 15 (as sppecified in schematic).

Where is a problem.

Thanks in advance.

Pavel. 

Parents

  • Andrew,

    I didn't touch my Cadence project since some weeks due to other more urgent job. Surprisingly when I came back today, I discovered that concerned feature doesn't work ! As one can constate from attached image, the value specified in schematic isn't taken in account, but default (specified in verilog module) instead. Where is a problem ? From accompagnied windowsit seems thatsettings are correct.

    Thanks in advance.

    Pavel.

Reply

  • Andrew,

    I didn't touch my Cadence project since some weeks due to other more urgent job. Surprisingly when I came back today, I discovered that concerned feature doesn't work ! As one can constate from attached image, the value specified in schematic isn't taken in account, but default (specified in verilog module) instead. Where is a problem ? From accompagnied windowsit seems thatsettings are correct.

    Thanks in advance.

    Pavel.

Children
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