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Virtuoso Autorouter Via Generation/Rules

dfick

I am using IC6.1.5-64b.500.9

I am using the LayoutGXL Space-Based Router. I have created the vias that I want the router to use and specified them in the constraints section of the tech file.The router uses them, but it modifies their enclosure. Is there a way to prevent this?

 I've tried searching google, the forums, and the documentation, but haven't been able to find anything.

 

 

 

Parents

  • I was able to fix the problem, although I did two things at once, so I'm not sure if the fix required one or both of the solution.

     First, I had defined DRC clean vias using stdViaDefs syntax in the ASCII  tech file (then loaded using CDW). I instead changed them to use the stdViaVariants syntax.

     Secondly, I defined the minOppExtension for the vias under the virtuosoDefaultExtractorSetup constraint group

     The second fix was definitely needed since the default vias were not DRC clean. Defining DRC clean vias was important, but I'm not sure how much the section matters.

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  • I was able to fix the problem, although I did two things at once, so I'm not sure if the fix required one or both of the solution.

     First, I had defined DRC clean vias using stdViaDefs syntax in the ASCII  tech file (then loaded using CDW). I instead changed them to use the stdViaVariants syntax.

     Secondly, I defined the minOppExtension for the vias under the virtuosoDefaultExtractorSetup constraint group

     The second fix was definitely needed since the default vias were not DRC clean. Defining DRC clean vias was important, but I'm not sure how much the section matters.

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