Stats

  • Locked Locked
  • Replies 6
  • Subscribers 127
  • Views 17914
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Assura LVS fail

Campo85

Hi everyone,

I have a problem to run Assura LVS in virtuoso. When I run the LVS, after a while, an alert box advise me that Assura fail. I attach the log file.

Thanks in advice for any reply

Stefano. 

Parents

  • I read the log file that you provided. It seems that the schematic you are using is not properly matched with the layout, that's why it is saying that the devices on schematic are not matched with the devices on layout and vice versa.

    I recommend you to use the following procedure:

    Option 1:

    Open your schematic, select Launch --> Layout XL --> press OK.

    In the new layout window select

    1. Connectivity --> Generate --> All from soruce

    2. Connectivity --> Nets --> Show/Hide selected incomplete nets

    Now make your layout and run the LVS

    Option 2:

    If you already did this please check following points in the Run LVS window:

    1. In the Schematic Design source section- "Library" should contain the name of the library in which your schematic is located

    "Cell" Should have the name of the cell (Schematic) in which you have designed the schematic.

    "View" Should have the text "Schematic"

    2. In the Layout Design source section- "Library" should contain the name of the library where the layout is located

    "Cell" Should contain the name of the cell (Layout) in which you have designed your layout.

    "View" Should have the text "Layout".

    This should solve your problem.

    Note: Before running LVS make sure that the options "Technology" should contain the same technology that u have used to design the schematic and the Extracted rule and Design rules have the correct destinations for the LVS to run properly.

Reply

  • I read the log file that you provided. It seems that the schematic you are using is not properly matched with the layout, that's why it is saying that the devices on schematic are not matched with the devices on layout and vice versa.

    I recommend you to use the following procedure:

    Option 1:

    Open your schematic, select Launch --> Layout XL --> press OK.

    In the new layout window select

    1. Connectivity --> Generate --> All from soruce

    2. Connectivity --> Nets --> Show/Hide selected incomplete nets

    Now make your layout and run the LVS

    Option 2:

    If you already did this please check following points in the Run LVS window:

    1. In the Schematic Design source section- "Library" should contain the name of the library in which your schematic is located

    "Cell" Should have the name of the cell (Schematic) in which you have designed the schematic.

    "View" Should have the text "Schematic"

    2. In the Layout Design source section- "Library" should contain the name of the library where the layout is located

    "Cell" Should contain the name of the cell (Layout) in which you have designed your layout.

    "View" Should have the text "Layout".

    This should solve your problem.

    Note: Before running LVS make sure that the options "Technology" should contain the same technology that u have used to design the schematic and the Extracted rule and Design rules have the correct destinations for the LVS to run properly.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.