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Layout XL connectivity for flattened transistors

How do I keep connectivity working properly when I flatten transistors? Specifically, the diffusion regions that are different nets but need to touch in order to form a transistor. If I draw two RX rectangles touching each other under a gate for the drain and source, then connectivity thinks I'm shorting the two rectangles together.

I'm currently using ic-5.1 but I had the same problem in the latest 6.1.5

Allan Wang over 12 years ago

Bump... I'd still like to know this...
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vvacad over 12 years ago

Hi Allan,
For 6.1.5, this is available using stop layer specifications, please refer to:
http://support.cadence.com/wps/PA_DocumentViewer/pubs/vxlhelp/vxlhelp6.1.5/chap2.html#extractorinfo
Also, the lxBlock* properties on shapes can be used to control the extraction. These properties (but not the stop layers) are also available in 5.1.x,
Thanks,
Vikram
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