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Specify a file path as a parameter type in Cadence VerilogAMS

uzzy
uzzy over 12 years ago

Hello,

        I am writing a verilogams module to be used in my spectre sims. When this module is instantiated in my schematic, it needs to take in a path to a pwl file as a parameter input to the verilogams instance and then incorporate this filename as the file type for the "vsource" instance defined inside the verilogams module. In short, this is something I want to do(syntax is incorrect) :

 parameter filename = "/projects/test.pwl";

 vsource #(.type("pwl"),.file(filename)) V1(p,n);

 I want to specify the particular pwl file to be used from the schematic and not by changing the verilogams code of the module. Any suggestions/comments will be greatly appreciated ?

Regards,

Uzzy 

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  • Andrew Beckett
    Andrew Beckett over 12 years ago

     First of all, are you running spectre or AMS as the simulator? If spectre, it will have to be a "veriloga" view, whereas AMS can use both veriloga and verilogams. I'm only asking because there's some differences in the implementation of string parameters between the two (for historical evolution reasons) and want to ensure I give the right answer...

    Andrew.

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  • uzzy
    uzzy over 12 years ago

    I am using the spectre simulator and it is a veriloga view that I am trying to simulate.

     Thanks,

    Uzzy 

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  • StephenB
    StephenB over 11 years ago

    Hi Andrew, I have exactly the same question.  I am simulating with spectre so I'm trying to get this to work in veriloga, although I'd also be interested to know how to do this with verilogams.  Can you please help?  Thanks so much!

     

    Stephen 

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Stephen,

    This works in both VerilogA and VerilogAMS:

    `include "disciplines.vams"

    module testpwl (plus,minus);

    inout plus,minus;
    electrical plus,minus;

    parameter filename="clock.pwl";

    vsource #(.type("pwl"),.file(filename)) V1(plus,minus);

    endmodule

    Spectre also works with:

     parameter string filename="clock.pwl";

    but this "string" keyword will not work in AMS Designer (Verilog AMS), so best to omit it in both.

    Regards,

    Andrew.

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