Stats

Locked Locked
Replies 1
Subscribers 125
Views 1308
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Strange "out of memory" error during verilog import

Hi,

I am trying to save myself the pain of connect 300+ pins by importing a verilog file instead. But I got the following error. Can anyone shed some light on this? I cannot find anything on documentation nor Google.

@(#)$CDS: ihdl.exe version 5.1.0 01/27/2011 00:14 (cicln04) $ Tue Oct 9 09:32:34 2012

Verilog definition for module xyz was not found. Using lib 'blahblahblah' cell 'xyz' view 'symbol' as its symbol.
Verilog definition for module abc was not found. Using lib 'blahblahblah' cell 'abc' view 'symbol' as its symbol.

Mismatch between existing view and view to be created for min_dig_sec
Checked in symbol min_dig_sec
Checked in functional view min_dig_sec. Expression on port found
VerilogIn: *F,45: Out of memory. Cannot allocate space.Exiting.
End of Logfile.

Andrew Beckett over 12 years ago

The size of what you're trying to import doesn't sound excessive. Please contact customer support (not that we'll be able to fix it in IC5141 since IC5141 has no more hotfixes (the release came out over 8 years ago) - you might want to try using the latest IC5141 hotfix first).
Andrew.
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.