BUS in extracted view

Hello,

I am simulating extracted view in ADEXL. I use OSS-based netlister to create netlist. Extracted view contains nets:

cnf_reg_analog<15>

cnf_reg_analog<14>

...

cnf_reg_analog<3>

I want to merge all nets to one bus as it is in my verilog netlist:

output [15:3] cnf_reg_analog;

but I got the message:

WARNING (VLOGNET-186): Unable to generate explicit netlist for the 'z_chip_def/cell/extracted_rc' cell view because split buses and/or bundle terminals are present in it.

Set the Terminal SyncUp option on the Netlist Setup form as 'Merge All' or set the hnlVerilogTermSyncUp variable as 'mergeAll' and netlist again.

And netlist looks like:

module cell (cnf_out, \cnf_reg_analog(15) , \cnf_reg_analog(14) ,

\cnf_reg_analog(13) , \cnf_reg_analog(12) , \cnf_reg_analog(11) ,

\cnf_reg_analog(10) , \cnf_reg_analog(9) , \cnf_reg_analog(8) ,

\cnf_reg_analog(7) , \cnf_reg_analog(6) , \cnf_reg_analog(5) ,

\cnf_reg_analog(4) , \cnf_reg_analog(3) , cnt_out, gnd, vdd, clk,

clk_cnt, cnf_en, cnf_in, cnt_in, hit, rst, shutter);

output cnf_out, \cnf_reg_analog(15) , \cnf_reg_analog(14) ,

\cnf_reg_analog(13) , \cnf_reg_analog(12) , \cnf_reg_analog(11) ,

\cnf_reg_analog(10) , \cnf_reg_analog(9) , \cnf_reg_analog(8) ,

\cnf_reg_analog(7) , \cnf_reg_analog(6) , \cnf_reg_analog(5) ,

\cnf_reg_analog(4) , \cnf_reg_analog(3) , cnt_out;

I tried to set hnlVerilogTermSyncUp to 'mergeAll', also to 'honorSM' without any effect. I can not find even SyncUp option in Netlist Setup.

I use:

IC06.15.506-615, MMSIM10.11.200, INCISIV10.20.026

Is there any solution how to create BUS from nets in extracted view?

Thank you very much for the answer.

Best Regards

Zdeno