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very long bit pattern for vbit source

Zitty

Hello,

 I want to test a mixed signal design in cadence virtuoso 6.1.5 with spectre.

To verify the functionallity of the digital part a very long input sequence, thousands of bits, is necessary.

I tried using the vbit source. What is very usefull about this is that it is possible to adjust the voltage levels as well as the length of one bit. This makes it superior over the vpwl  at least for my application.

I found a helpful document that makes it possible to adjust the properties of vbit in a way that it is possible to insert a design variable for the data . Another document helped me to load a bitstream from a tex-file into this design variable inside ade-l. 

The problem is that this is only possible for short bitstreams. At least my bitstream is too long for such a proceeding.

Is there any other approach to solve this problem?

A stimulus file would also be very long/large...

 

regards Zitty 

Parents

  • Do you need a specific bit pattern, or would a psudeo random bit pattern be OK?

    I created a verilog-A module which generates a PRBS 2^15 - 1 bit pattern.

    Bit period can be set via a clock input signal, or with a verilog-a "timer" event generator.

    Output amplitude can be set by a parameter, or by pwr/gnd input pins.

     Hope this is helpfull.

    Tony

Reply

  • Do you need a specific bit pattern, or would a psudeo random bit pattern be OK?

    I created a verilog-A module which generates a PRBS 2^15 - 1 bit pattern.

    Bit period can be set via a clock input signal, or with a verilog-a "timer" event generator.

    Output amplitude can be set by a parameter, or by pwr/gnd input pins.

     Hope this is helpfull.

    Tony

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