I want to test a mixed signal design in cadence virtuoso 6.1.5 with spectre.
To verify the functionallity of the digital part a very long input sequence, thousands of bits, is necessary.
I tried using the vbit source. What is very usefull about this is that it is possible to adjust the voltage levels as well as the length of one bit. This makes it superior over the vpwl at least for my application.
I found a helpful document that makes it possible to adjust the properties of vbit in a way that it is possible to insert a design variable for the data . Another document helped me to load a bitstream from a tex-file into this design variable inside ade-l.
The problem is that this is only possible for short bitstreams. At least my bitstream is too long for such a proceeding.
Is there any other approach to solve this problem?
A stimulus file would also be very long/large...
OK, this isn't entirely trivial. Follow these steps:
What the above is doing is getting the data parameter netlisted as a normal parameter (the netlist procedure that is usually used adds quotes around it, but in this case you don't want the quotes so that the value can be interpreted as a spectre parameter), and then you are ensuring the the netlist ends up with quotes around the parameter value. For example, here's my netlist:
simulator lang=spectreglobal 0parameters mypat="10010101"// Library name: mylib// Cell name: testbit// View name: schematicR0 (op 0) resistor r=1KV0 (op 0) vsource val1=1 val0=0 data=mypat delay=0 rise=1n fall=1n \ period=20n type=bit