Stats

  • Locked Locked
  • Replies 13
  • Subscribers 126
  • Views 35455
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

very long bit pattern for vbit source

Zitty

Hello,

 I want to test a mixed signal design in cadence virtuoso 6.1.5 with spectre.

To verify the functionallity of the digital part a very long input sequence, thousands of bits, is necessary.

I tried using the vbit source. What is very usefull about this is that it is possible to adjust the voltage levels as well as the length of one bit. This makes it superior over the vpwl  at least for my application.

I found a helpful document that makes it possible to adjust the properties of vbit in a way that it is possible to insert a design variable for the data . Another document helped me to load a bitstream from a tex-file into this design variable inside ade-l. 

The problem is that this is only possible for short bitstreams. At least my bitstream is too long for such a proceeding.

Is there any other approach to solve this problem?

A stimulus file would also be very long/large...

 

regards Zitty 

Parents

  • OK, this isn't entirely trivial. Follow these steps:

    1. Copy the vbit source from analogLib into your own library, and call it vbitparam (make sure it's not called "vbit" as there is a check in the netlist procedure for being called vbit, which will defeat the next step)
    2. Tools->CDF->Edit CDF and edit the "Base" CDF for the new vbitparam cell.
    3. Go to the Simulation Information section, and select "spectre" as the simulator.
    4. Remove "data" from the otherParameters section, and add it to the instParameters section
    5. OK all the CDF editing forms
    6. In your schematic, use the vbitparam component instead of vbit and set the "Pattern parameter data" parameter to be the name of the design variable you want.
    7. In ADE or OCEAN, create a design variable with the same name as the design variable, and set the value to "p1,p2,p3" (with the quotes specified). In OCEAN this would be:
      desVar("myparam" "\"p1,p2,p3\"")

     

    What the above is doing is getting the data parameter netlisted as a normal parameter (the netlist procedure that is usually used adds quotes around it, but in this case you don't want the quotes so that the value can be interpreted as a spectre parameter), and then you are ensuring the the netlist ends up with quotes around the parameter value. For example, here's my netlist:

    simulator lang=spectre
    global 0
    parameters mypat="10010101"

    // Library name: mylib
    // Cell name: testbit
    // View name: schematic
    R0 (op 0) resistor r=1K
    V0 (op 0) vsource val1=1 val0=0 data=mypat delay=0 rise=1n fall=1n \
            period=20n type=bit

     

    Kind Regards,

    Andrew.

Reply

  • OK, this isn't entirely trivial. Follow these steps:

    1. Copy the vbit source from analogLib into your own library, and call it vbitparam (make sure it's not called "vbit" as there is a check in the netlist procedure for being called vbit, which will defeat the next step)
    2. Tools->CDF->Edit CDF and edit the "Base" CDF for the new vbitparam cell.
    3. Go to the Simulation Information section, and select "spectre" as the simulator.
    4. Remove "data" from the otherParameters section, and add it to the instParameters section
    5. OK all the CDF editing forms
    6. In your schematic, use the vbitparam component instead of vbit and set the "Pattern parameter data" parameter to be the name of the design variable you want.
    7. In ADE or OCEAN, create a design variable with the same name as the design variable, and set the value to "p1,p2,p3" (with the quotes specified). In OCEAN this would be:
      desVar("myparam" "\"p1,p2,p3\"")

     

    What the above is doing is getting the data parameter netlisted as a normal parameter (the netlist procedure that is usually used adds quotes around it, but in this case you don't want the quotes so that the value can be interpreted as a spectre parameter), and then you are ensuring the the netlist ends up with quotes around the parameter value. For example, here's my netlist:

    simulator lang=spectre
    global 0
    parameters mypat="10010101"

    // Library name: mylib
    // Cell name: testbit
    // View name: schematic
    R0 (op 0) resistor r=1K
    V0 (op 0) vsource val1=1 val0=0 data=mypat delay=0 rise=1n fall=1n \
            period=20n type=bit

     

    Kind Regards,

    Andrew.

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.