Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 14223
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Schematic p-cell for modelling parasitic resistance and capacitance

tmart

Hi, 

I'm looking for a schematic p-cell which models parasitic resistance and capacitance in layout.

A former employer of mine had this function; to model a metal wire or interconnect in the layout, you'd place a special p-cell in your schematic, enter in which metal layer it was placed, add length and width as well as surrounding density, and the p-cell would pop out with a calculated RC value and act as a lumped resistor and capacitor. This was incredibly efficient in pre-layout simulation of routing-sensitive modules.

Is there built-in support in Cadence for such a function, or will I have to write a p-cell from scratch myself? 

Best regards, 

Tore

Parents Reply Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.