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issue on noise from resistor modelled by ahdl

eesm

Do I need to turn on an option or options to allow resistor, which is modelled by the ahdl code, to generate noise in noise simuation in ADE environment?

I just simply injecting a current from an ideal current source to that ahdl modelled resistor but I cannot get any 4KTR noise.

I did try to replace that resistor by an resistor from analogLib and run noise sim, I can successfully get the 4KTR noise.

Please help

Thanks 

  • You'd need to use the white_noise function in VerilogA to do this. Look at the Verilog-A Language Reference manual and search through for white_noise - where it's described there's even an example of how you'd code the 4KTR noise.

    <MMSIMinstDir>/doc/veriaref/veriaref.pdf

    Regards,

    Andrew.

  • The code is provided and I do check it has the white_noise function there, but I still get ZERO noise output.  This makes me think of what I miss in the whole process.

    Any hint or information you need?

    Thanks Andrew 

  • Which analysis are you using? (And which simulator and which version?)

    I can't think in general why noise from white_noise would not appear unless the model has been coded badly or you've explicitly turned off the noise on the Simulator->Options->Analog form (which seems unlikely)

    Andrew

  • I am running "noise" analysis.  I am using Spectre and the version is 10.1.1.441.isr25 32 bit.

    In the analog form, where can I see the noise is explicitly switched off?

    Thanks 

  •  I've attached the Simulation->Options->Analog (Main Tab, scrolled to the bottom). Note that this is only in IC615 (I think). If nothing is selected, all noise sources will be on.

    As I said, it's unlikely this is it though. Probably best if you contact customer support and then you can send them your example netlist (say). Or maybe you can post it here (assuming it's yours to post and is not somebody else's IP).

    Regards,

    Andrew.

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