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Verilog-A Monte-Carlo simulations

eppo

 Hi all,

 I would like to performe Monte-Carlo simulations by using my own transistor model developped in verilog-A language.

 For this, I added the line below in the code in order to vary the parameter "CMC" (CMC is a new parameter)

(*cds_inherited_parameter*) parameter real CMC=0.0;  

also in the file.scs I have added the sequence below :

  parameters CMC

statistics {
   mismatch {
      vary CMC dist=gauss std=0.001a
      }
      }

 When i try to run simulation i have the following errors :

ERROR (SFE-3): `BMA_MODEL' is being redefined.

WARNING (SFE-30): "input.scs" 15: I1: `CMC' is not a valid parameter for an instance of `BMA_MODEL'.  Ignored

ERROR (SFE-1997): "input.scs" 15: I1: parameter `CMC': Unknown parameter name `CMC' found in expression.  

I guess the procedure that I use is wrong. How can I introduce variations of parameters model and then running Monte-carlo simulation?

Thanks, 

  • The error suggests that BMA_MODEL is defined more than once. The warning then suggests that whatever BMA_MODEL you have, it does not have a parameter CMC. And the last error is probably because no value is defined for CMC on the parameters statement.

    It's really hard to tell without seeing your complete setup. If you can't provide that here, I'd suggest logging a service request.

    Regards,

    Andrew.

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