i had drawn the schemaic for nand gate using 3-terminal nmos &pmos.
i had drawn the automatic layout from the schematic.
when i do the DRC ,there is no error.
but if i do the lvs it shows some mismatches.
Do you have a question? Whilst I'm sure everyone is interested in what you've been working on, I presume you've got some issue that you want some assistance with. I suggest you read the forum guidelines and ensure you provide sufficient information for anyone to be able to help you.
check out the pins like vdd,gnd, in and out. all are at proper place or not