Making a monte carlo simulation component specific

Yes. Type "spectre -h montecarlo" and you'll see:

10      ignore=[...]      If set, no variation is applied to specified subcircuit instances. In
                          addition, all subcircuits instantiated under this instance do not have
                          variation enabled. By default, mismatch is applied to all subcircuit
                          instances in the design and the process is applied globally.

So you can specify on the montecarlo analysis statement ignore=[I1 I2 I3] etc.

Andrew.

Hi Andrew, I have one quick question related to this: does it also apply to process variations? In IC615, we can specify the instance for mismatch in ADE XL "Run Monte Carlo Sampling", however, there's no option for process. Therefore, if I want to ignore PV for specific instances in my test bench, how can I do that? Thanks!

Hi Andrew, I have one quick question related to this: does it also apply to process variations? In IC615, we can specify the instance for mismatch in ADE XL "Run Monte Carlo Sampling", however, there's no option for process. Therefore, if I want to ignore PV for specific instances in my test bench, how can I do that? Thanks!

Not currently. There's a change request (CCR 2017541) related to this in the system, but it's not been implemented yet (I think spectre may have the capability - although there are some slight gaps at the moment - but it's not available through the user interface, even in the current IC618 release rather than the rather old version you're using).

Regards,

Andrew.

Hi Andrew, thanks for the quick reply, you're amazing!

Hi Andrew,
Is there any update on this front (specifying instances of a testbench on corner simulation using ADEXL)? I am on IC618. Thanks!

Not entirely sure specifically what you want. Have you checked the Monte Carlo options form (this is from Assembler, and. you should really be using that rather than ADE XL):

The Variation/Selected/Unselected give quite a few choices as to what is enabled/disabled for different parts of the circuit.

Andrew

Hi Andrew,

Thank you for your reply.

It seems to me that the options you have shared above could also be done in ADEXL (run->Monte Carlo Sampling …). However, I will explore the assembler tool in-depth. 

Perhaps, my question was not very clear. 
I have a testbench with four circuit blocks and some test signals. I wanted to simulate the variation of an output of one of the blocks when the transistors of that particular block are running at different process corners. Simulataneously, I would like to run the other three blocks on typical process corner. In MC simulation, we are able to select the blocks for which we want the variations to be activated the way you showed it above. Would a similar thing be possible for corner simulation?
Thank you again.

This is a slightly odd requirement, unless you're trying to model the situation where the blocks are on different chips - because they won't be in different process corners in reality.

If that's the case, you can do this with the "MTS" options (right mouse button->MTS Options over the test) and then in the popup form you can enable MTS for the block or instance in question, and then in the Models column specify the model file and corner you wish to use for that block. This requires the top level to be a config BTW. 

With ADE XL this requires two ADE GXL tokens to do this, but if you're using ADE Assembler, it's included in the Assembler license. The idea is that this "MTS" (Multi-Technology Support) allows for using identically named models (from the same or a different technology) in different blocks in the design - the resulting netlist is scoped to include the models, temperature settings etc in that block.

Is that what you want?

Andrew.

Hi Andrew,
The task is limited to simulation and verification of a particular IP in its "natural" environment. It was easier to instantiate the blocks that would be connected with the IP than using, say, analogLib test signals. It helps to activate the process variations only for that IP to determine how good it is designed without taking the effect of its neighboring blocks into account and without changing the task into top level verification.
I have Assembler license. Thank you for the solution. It is exactly what I was looking for.
Regards,

Hi Andrew,

I’m currently trying to see the Mismatch variation from a transistor pair in a subblock (/BLOCK/SUBBLOCK/M0, /BLOCK/SUBBLOCK/M1)

I have selected the transistor pair and set the Variation to ‘Mismatch’, the Selected to ‘Mismatch’ and the Unselected to ‘No Variation’.

However, this produces NO variation on my output. If instead I only select my top block, I do get variations so I would assume that everything else is setup correctly.

I’m using IC6.1.8-64b.500.16

Do you know if there are some limitations or bugs in this feature ?

 /Henrik

Henrik,

Please contact customer support. I think we may need to take a look, particularly it might be necessary to know which PDK you're using in case this has some dependency on the models. I would expect this to work (it did in the example I just tried)

Andrew

Ok, thanks for testing it out.

/Henrik