Layout problem with nMOS transistors N_BPW_12_LLNVT 65 nm UMC

Hi everybody,

I am having a problem with transistors nMOS model N_BPW_12_LLNVT in 65 nm UMC.

These transistors are triple-well. This is the first time I am using them and although my layout passes the DRC rules and
the LVS, when I simulate it in post-layout level, the DC voltages of my circuit goes to values different than the ones obtained
in schematic level. I suppose I am connecting wrong any of the wells of the transistor.

Has anyone used this kind of transistors or any triple well technology? I would like to know how I have to bias it.
I want to used the bulk as an input.

Thanks in advance.