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Terminal Mismatch for MOS_a2d in virtuoso

Hi, I am trying to run mixed signal simulations using ultrasim in Virtuoso 6.15. The test design is very simple and contains a vpulse (from analogLib) followed by MOS_a2d (from analogLib) which is followed by a buffer (written in verilog). when i try to simulate the design using ultrasim, following error occurs:

Error found by UltraSim during initializing the design.
    ERROR (USIMDB-11702): The UltraSim simulator detected a node mismatch error
        in the model 'a2d' in instance 'I3', in top level circuit.
        ( terminal mismatch 0 should be between [2,2] ).

instance I3 is MOS_a2d. how can this issue be resolved?

Quek over 12 years ago

Hi Arslan

A similar issue was described in COS article 11633708, this issue has already been fixed IUS92-s015. Would you please try a higher version of IUS or INCISIVE package and let us know if it resolves the problem?

Best regards
Quek
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Andrew Beckett over 12 years ago

Also, I'm assuming you're using UltrasimVerilog rather than Ultrasim?
Andrew.
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