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QRC's av_extracted view is not showing any metal layers

pavan7kumar

 Hello all,
             I designed simple inverter using UMC65ll kit and it passed successfully in DRC, LVS, and QRC. But extracted view of this design isn't showing any metal layer instead schematic of transistor is shown (figure attached). I have also ran QRC by setting valid layers (LSW->edit->set valid layers->set all valid) but problem still remains the same. Moreover, I am only using METAL1, DIFFUSION and POLY1 layers. Versions are as follows.

IC 614-06.14-512
Assura 4.1 USR2 with EXT101 &
MMSIM 0720.593
How can I set up this to show layers in av_extracted view?



Regards,

Pavan.

Parents

  •  I tried with "saveRecognition"but it doesnt work berndfi. In extract.rul I could only find "saveProperty" (in UMC65). But in GPDK180nm, I found lines such as

    saveInterconnect((M6term "Metal6"))
    saveInterconnect((M5term "Metal5"))
    saveInterconnect((M4term "Metal4"))
    saveInterconnect((M3term "Metal3"))
    saveInterconnect((M2term "Metal2"))
    saveInterconnect((M1term "Metal1"))
    saveInterconnect((NSDterm "Nimp"))
    saveInterconnect((PSDterm "Pimp"))
    saveInterconnect((NWELLterm "Nwell"))
    saveInterconnect((CapMetal "CapMetal"))
    saveInterconnect((INDterm1 "INDdummy"))
    saveInterconnect((INDterm2 "INDdummy"))
    saveInterconnect((POLYterm "Poly"))
    saveInterconnect((JVARanode "JVAR1dummy"))
    saveInterconnect((Pwell "Pwell"))
    saveInterconnect((ISOPWELL "Nburied"))
    saveInterconnect((Nburied "Nburied"))

    But i am not understanding how they mentioned layers and what it means to. 

    From library I have only used only tt_ll_rvt and it is not showing any warning about this. So i think this is not an issue.

     

     

    Regards,

    Pavan.

     

     

Reply

  •  I tried with "saveRecognition"but it doesnt work berndfi. In extract.rul I could only find "saveProperty" (in UMC65). But in GPDK180nm, I found lines such as

    saveInterconnect((M6term "Metal6"))
    saveInterconnect((M5term "Metal5"))
    saveInterconnect((M4term "Metal4"))
    saveInterconnect((M3term "Metal3"))
    saveInterconnect((M2term "Metal2"))
    saveInterconnect((M1term "Metal1"))
    saveInterconnect((NSDterm "Nimp"))
    saveInterconnect((PSDterm "Pimp"))
    saveInterconnect((NWELLterm "Nwell"))
    saveInterconnect((CapMetal "CapMetal"))
    saveInterconnect((INDterm1 "INDdummy"))
    saveInterconnect((INDterm2 "INDdummy"))
    saveInterconnect((POLYterm "Poly"))
    saveInterconnect((JVARanode "JVAR1dummy"))
    saveInterconnect((Pwell "Pwell"))
    saveInterconnect((ISOPWELL "Nburied"))
    saveInterconnect((Nburied "Nburied"))

    But i am not understanding how they mentioned layers and what it means to. 

    From library I have only used only tt_ll_rvt and it is not showing any warning about this. So i think this is not an issue.

     

     

    Regards,

    Pavan.

     

     

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